[Pdbg] [PATCH] p8chip: Enable SRESET for P8

Artem Senichev artemsen at gmail.com
Tue Feb 5 19:30:56 AEDT 2019

On Tue, Feb 05, 2019 at 01:17:59PM +1100, Alistair Popple wrote:
> How well does this actually work for you?

As Nick said (from https://lists.ozlabs.org/pipermail/openpower-firmware/2018-April/000220.html),

> On P8 we can actually send a sreset,
> but the SRR1 register may end up being incorrect. This means we can not
> return from the interrupt and continue, but we should be able to go on
> to take a crash dump and restart the machine.

So, it really works for us. On the BMC side, we do following steps:
1. Disable OCC (we use their I2C channel to communicate with the host's CPU):
   occ-active.sh disable
2. Stop watchdog service to prevent host reboot:
   systemctl stop phosphor-watchdog at poweron.service
3. Send SRESET signal:
   pdbg --backend=i2c --device=/dev/i2c-4 -p 0 -c 1 -t 0 sreset

Also, we have a small patch for skiboot, that modifies several lines
in file core/direct-controls.c:
-	if (proc_gen != proc_gen_p9)
+	if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8)

Artem Senichev
Software Engineer, YADRO.

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