[Pdbg] [PATCH] libpdbg/p9chip: use SPWKUP_FSP instead of SPWKUP_OTR

[Nicholas Piggin]

Dean Sanner notes that pdbg should not use the OTR special wakeup
register, as it is used by the PM complex (i.e., SGPE, CME, PGPE).
It should use the FSP register instead, which is reserved for service
processor firmware, and nothing else in OpenBMC uses this at the
moment.

In theory when pdbg is used via the host, it should be using the HYP
register via some OPAL arbitration mechanism (OPAL being the owner of
the HYP register), but in the absence of any of that mechanism, FSP
is the best option.

Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
---
 libpdbg/p9chip.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libpdbg/p9chip.c b/libpdbg/p9chip.c
index c5de3bb..3a7ff8a 100644
--- a/libpdbg/p9chip.c
+++ b/libpdbg/p9chip.c
@@ -71,7 +71,7 @@
 #define  NET_CTRL0_FENCE_EN 		PPC_BIT(18)
 #define NET_CTRL0_WOR	0xf0042
 #define PPM_GPMMR	0xf0100
-#define PPM_SPWKUP_OTR	0xf010a
+#define PPM_SPWKUP_FSP	0xf010b
 #define PPM_SSHOTR	0xf0113
 #define  SPECIAL_WKUP_DONE PPC_BIT(1)
 
@@ -468,7 +468,7 @@ static int p9_core_probe(struct pdbg_target *target)
 	if (!(value & NET_CTRL0_CHIPLET_ENABLE))
 		return -1;
 
-	CHECK_ERR(pib_write(target, PPM_SPWKUP_OTR, PPC_BIT(0)));
+	CHECK_ERR(pib_write(target, PPM_SPWKUP_FSP, PPC_BIT(0)));
 	do {
 		usleep(1000);
 		CHECK_ERR(pib_read(target, PPM_SSHOTR, &value));
@@ -486,7 +486,7 @@ static int p9_core_probe(struct pdbg_target *target)
 static void p9_core_release(struct pdbg_target *target)
 {
 	usleep(1); /* enforce small delay before and after it is cleared */
-	pib_write(target, PPM_SPWKUP_OTR, 0);
+	pib_write(target, PPM_SPWKUP_FSP, 0);
 	usleep(10000);
 }
 
-- 
2.17.0