[PATCH v4 2/9] dt-bindings: PCI: Add ASPEED PCIe RC support

[Jacky Chou]

Thank you for your reply.

> > +  The ASPEED PCIe Root Complex controller provides PCI Express Root
> > +Complex
> > +  functionality for ASPEED SoCs, such as the AST2600 and AST2700.
> > +  This controller enables connectivity to PCIe endpoint devices,
> > +supporting
> > +  memory and I/O windows, MSI and legacy interrupts, and integration
> > +with
> > +  the SoC's clock, reset, and pinctrl subsystems. On AST2600, the
> > +PCIe Root
> > +  Port device number is always 8.
> 
> s/legacy/INTx/
> 

Agreed.

> > +properties:
> > +  compatible:
> > +    enum:
> > +      - aspeed,ast2600-pcie
> > +      - aspeed,ast2700-pcie
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  ranges:
> > +    minItems: 2
> > +    maxItems: 2
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +    description: IntX and MSI interrupt
> 
> s/IntX/INTx/
> 

Agreed.

> > +    pcie0: pcie at 1e770000 {
> > +      compatible = "aspeed,ast2600-pcie";
> > +      device_type = "pci";
> > +      reg = <0x1e770000 0x100>;
> > +      #address-cells = <3>;
> > +      #size-cells = <2>;
> > +      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> > +      bus-range = <0x00 0xff>;
> > +
> > +      ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0
> 0x00008000
> > +                0x02000000 0x0 0x60000000 0x60000000 0x0
> 0x20000000>;
> > +
> > +      resets = <&syscon ASPEED_RESET_H2X>;
> > +      reset-names = "h2x";
> > +      pinctrl-0 = <&pinctrl_pcierc1_default>;
> > +      pinctrl-names = "default";
> > +
> > +      #interrupt-cells = <1>;
> > +      msi-controller;
> > +
> > +      aspeed,ahbc = <&ahbc>;
> > +
> > +      interrupt-map-mask = <0 0 0 7>;
> > +      interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> > +                      <0 0 0 2 &pcie_intc0 1>,
> > +                      <0 0 0 3 &pcie_intc0 2>,
> > +                      <0 0 0 4 &pcie_intc0 3>;
> > +      legacy-interrupt-controller {
> > +        interrupt-controller;
> > +        #address-cells = <0>;
> > +        #interrupt-cells = <1>;
> > +      };
> 
> IIUC, Rob says there's no need for a separate interrupt-controller stanza and it
> can be directly in the host bridge [1].
> 
> I think that does make interrupt-map a little more verbose because the parent
> unit address will use the host bridge #address-cells (3) instead of the interrupt
> controller #address-cells (0), e.g., this from [2]:
> 
>   pcie at 10e40000 {
>       compatible = "renesas,r9a08g045-pcie";
>       #address-cells = <3>;
>       #interrupt-cells = <1>;
>       interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
>                       <0 0 0 2 &pcie 0 0 0 1>, /* INTB */
>                       <0 0 0 3 &pcie 0 0 0 2>, /* INTC */
>                       <0 0 0 4 &pcie 0 0 0 3>; /* INTD */
> 
> [1]
> https://lore.kernel.org/linux-pci/20250509204905.GA4080349-robh@kernel.or
> g/
> [2]
> https://lore.kernel.org/linux-pci/20251007133657.390523-2-claudiu.beznea.uj
> @bp.renesas.com/

Thank you for your information.
I will modify this part in next version.

Thanks,
Jacky