[PATCH v6 0/7] Add ASPEED PCIe Root Complex support

[Rob Herring]

On Fri, Dec 05, 2025 at 12:12:35AM +0000, Jacky Chou wrote:
> Hi Rob,
> 
> Thanks for your comments.
> 
> > > Changes in v6:
> > > - Refer to pci-cpi-bridge.yaml to update aspeed,ast2600-pcie.yaml and
> > >   the pcie node of aspeed-g6.dtsi.
> > 
> > Where is this? You don't describe the root port and its properties at all now.
> > 
> 
> May I confirm whether the pcie at 8,0 in aspeed-g6.dtsi is not considered the 
> root port? From my understanding, that node represents the root port, so I 
> want to make sure I'm aligning with your expectation before updating the binding.

I believe you told me it was the root port.

> Could you help clarify how you would like the root port and its properties to 
> be described in the schema?

properties:
  pcie at 8,0:
    $ref: /schemas/pci/pci-pci-bridge.yaml#
    unevaluatedProperties: false

    properties:

And then add all the properties you have which are not defined in 
pci-pci-bridge.yaml (and pci-device.yaml by reference) (i.e. clocks, 
resets, phys, etc.).

Rob