[PATCH u-boot, v2019.04-aspeed-openbmc v1 2/3] gpio: add aspeed-sgpio controller

Dmitriy Sharikhin d.sharikhin at yadro.com
Thu May 16 02:06:03 AEST 2024


This patch brings support for Aspeed Serial GPIO controller
in AST2500/AST2600 targets. Driver is based on Linux Kernel
driver written by American Megatrends International.

Signed-off-by: Dmitrii Sharikhin <d.sharikhin at yadro.com>
---
 drivers/gpio/Kconfig        |   5 +
 drivers/gpio/Makefile       |   1 +
 drivers/gpio/aspeed_sgpio.c | 324 ++++++++++++++++++++++++++++++++++++
 3 files changed, 330 insertions(+)
 create mode 100644 drivers/gpio/aspeed_sgpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 69ca18c15b..a3f5c626e6 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -83,6 +83,11 @@ config ASPEED_GPIO
 	help
 	  This driver supports the Aspeed GPIO controller
 
+config ASPEED_SGPIO
+	bool "Aspeed Serial GPIO Driver"
+	help
+	  This driver supports the Aspeed SGPIO controller
+
 config DA8XX_GPIO
 	bool "DA8xx GPIO Driver"
 	help
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c9a47bfd51..e754a70c7b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_)DM_PCA953X)	+= pca953x_gpio.o
 obj-$(CONFIG_DM_74X164)		+= 74x164_gpio.o
 
 obj-$(CONFIG_ASPEED_GPIO) += aspeed_gpio.o
+obj-$(CONFIG_ASPEED_SGPIO) += aspeed_sgpio.o
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
 obj-$(CONFIG_BCM6345_GPIO)	+= bcm6345_gpio.o
diff --git a/drivers/gpio/aspeed_sgpio.c b/drivers/gpio/aspeed_sgpio.c
new file mode 100644
index 0000000000..6b28a9e9a9
--- /dev/null
+++ b/drivers/gpio/aspeed_sgpio.c
@@ -0,0 +1,324 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2024, KNS Group LLC (YADRO)
+ *
+ * This driver is based on Linux Kernel driver by
+ * Copyright 2019 American Megatrends International LLC.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <config.h>
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+
+#define ASPEED_SGPIO_CTRL		0x54
+
+#define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
+#define ASPEED_SGPIO_ENABLE		BIT(0)
+#define ASPEED_SGPIO_PINS_SHIFT		6
+
+struct aspeed_sgpio_pdata {
+	const u32 pin_mask;
+	const u32 clk_id;
+};
+
+struct aspeed_sgpio_priv {
+	void *regs;
+};
+
+struct aspeed_sgpio_bank {
+	u16 val_regs;
+	u16 rdata_reg;
+	u16 irq_regs;
+	u16 tolerance_regs;
+	const char names[4][3];
+};
+
+/*
+ * Note: The "value" register returns the input value when the GPIO is
+ *	 configured as an input.
+ *
+ *	 The "rdata" register returns the output value when the GPIO is
+ *	 configured as an output.
+ */
+static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
+	{
+		.val_regs = 0x0000,
+		.rdata_reg = 0x0070,
+		.irq_regs = 0x0004,
+		.tolerance_regs = 0x0018,
+		.names = { "A", "B", "C", "D" },
+	},
+	{
+		.val_regs = 0x001C,
+		.rdata_reg = 0x0074,
+		.irq_regs = 0x0020,
+		.tolerance_regs = 0x0034,
+		.names = { "E", "F", "G", "H" },
+	},
+	{
+		.val_regs = 0x0038,
+		.rdata_reg = 0x0078,
+		.irq_regs = 0x003C,
+		.tolerance_regs = 0x0050,
+		.names = { "I", "J", "K", "L" },
+	},
+	{
+		.val_regs = 0x0090,
+		.rdata_reg = 0x007C,
+		.irq_regs = 0x0094,
+		.tolerance_regs = 0x00A8,
+		.names = { "M", "N", "O", "P" },
+	},
+};
+
+enum aspeed_sgpio_reg {
+	reg_val,
+	reg_rdata,
+	reg_irq_enable,
+	reg_irq_type0,
+	reg_irq_type1,
+	reg_irq_type2,
+	reg_irq_status,
+	reg_tolerance,
+};
+
+#define GPIO_VAL_VALUE		(0x00)
+#define GPIO_IRQ_ENABLE		(0x00)
+#define GPIO_IRQ_TYPE0		(0x04)
+#define GPIO_IRQ_TYPE1		(0x08)
+#define GPIO_IRQ_TYPE2		(0x0C)
+#define GPIO_IRQ_STATUS		(0x10)
+
+#define GPIO_BANK(x)		((x) >> 6)
+#define GPIO_OFFSET(x)		((x) & GENMASK(5, 0))
+#define GPIO_BIT(x)		BIT(GPIO_OFFSET(x) >> 1)
+
+/* This will be resolved at compile time */
+static inline void __iomem *bank_reg(struct aspeed_sgpio_priv *gpio,
+					const struct aspeed_sgpio_bank *bank,
+					const enum aspeed_sgpio_reg reg)
+{
+	switch (reg) {
+	case reg_val:
+		return gpio->regs + bank->val_regs + GPIO_VAL_VALUE;
+	case reg_rdata:
+		return gpio->regs + bank->rdata_reg;
+	case reg_irq_enable:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE;
+	case reg_irq_type0:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0;
+	case reg_irq_type1:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1;
+	case reg_irq_type2:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE2;
+	case reg_irq_status:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_STATUS;
+	case reg_tolerance:
+		return gpio->regs + bank->tolerance_regs;
+	default:
+		/* acturally if code runs to here, it's an error case */
+		BUG();
+	}
+}
+
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+{
+	unsigned int bank = GPIO_BANK(offset);
+
+	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
+	return &aspeed_sgpio_banks[bank];
+}
+
+static inline bool aspeed_sgpio_is_input(unsigned int offset)
+{
+	return !(offset & 0x1);
+}
+
+static int aspeed_sgpio_get_value(struct udevice *dev, unsigned offset)
+{
+	struct aspeed_sgpio_priv *priv = dev_get_priv(dev);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+
+	return !!(readl(
+		bank_reg(priv, bank,
+			aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata))
+			& GPIO_BIT(offset));
+}
+
+static int aspeed_sgpio_set_value(struct udevice *dev, unsigned offset,
+					int value)
+{
+	struct aspeed_sgpio_priv *priv;
+	const struct aspeed_sgpio_bank *bank;
+	u32 data;
+
+	if (aspeed_sgpio_is_input(offset))
+		return -EINVAL;
+
+	priv = dev_get_priv(dev);
+	bank = to_bank(offset);
+	data = readl(bank_reg(priv, bank, reg_rdata));
+
+	if (value)
+		data |= GPIO_BIT(offset);
+	else
+		data &= ~GPIO_BIT(offset);
+
+	writel(data, bank_reg(priv, bank, reg_val));
+
+	return 0;
+}
+
+static int aspeed_sgpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (offset >= uc_priv->gpio_count)
+		return -ENODEV;
+
+	if (!aspeed_sgpio_is_input(offset))
+		return -EOPNOTSUPP;
+
+	return 0;
+}
+
+static int aspeed_sgpio_direction_output(struct udevice *dev, unsigned offset,
+						int value)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (offset >= uc_priv->gpio_count)
+		return -ENODEV;
+
+	if (aspeed_sgpio_is_input(offset))
+		return -EOPNOTSUPP;
+
+	return aspeed_sgpio_set_value(dev, offset, value);
+}
+
+static int aspeed_sgpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (offset >= uc_priv->gpio_count)
+		return -ENODEV;
+
+	if(aspeed_sgpio_is_input(offset))
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static const struct dm_gpio_ops sgpio_aspeed_ops = {
+	.direction_input = aspeed_sgpio_direction_input,
+	.direction_output = aspeed_sgpio_direction_output,
+	.get_value = aspeed_sgpio_get_value,
+	.set_value = aspeed_sgpio_set_value,
+	.get_function = aspeed_sgpio_get_function,
+};
+
+static int aspeed_sgpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct aspeed_sgpio_priv *priv = dev_get_priv(dev);
+	const struct aspeed_sgpio_pdata *pdata =
+		(const struct aspeed_sgpio_pdata *) dev_get_driver_data(dev);
+	struct clk clk;
+	u32 nr_gpios;
+	u32 sgpio_freq = 2000000;
+	u32 sgpio_clk_div;
+	u32 apb_freq;
+	u32 gpio_cnt_regval;
+	int ret;
+
+	uc_priv->bank_name = dev->name;
+	ofnode_read_u32(dev_ofnode(dev), "ngpios", &nr_gpios);
+	ofnode_read_u32(dev_ofnode(dev), "bus-frequency", &sgpio_freq);
+	if (sgpio_freq == 0)
+		return -EINVAL;
+
+	/*
+	 * From the datasheet,
+	 *	SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
+	 *	period = 2 * (GPIO254[31:16] + 1) / PCLK
+	 *	frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
+	 *	frequency = PCLK / (2 * (GPIO254[31:16] + 1))
+	 *	frequency * 2 * (GPIO254[31:16] + 1) = PCLK
+	 *	GPIO254[31:16] = PCLK / (frequency * 2) - 1
+	 */
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0) {
+		pr_warn("%s: Can't get clock for %s: %d\n", __func__, dev->name,
+		      ret);
+	}
+
+	apb_freq = clk_get_rate(&clk);
+	clk_free(&clk);
+
+	if (IS_ERR_VALUE(apb_freq)) {
+		pr_warn("aspeed-sgpio failed to get clock\n");
+		return ret;
+	}
+
+	sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
+	if (!FIELD_FIT(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div)) {
+		pr_warn("aspeed-sgpio clock is not representable\n");
+		return -EINVAL;
+	}
+
+	priv->regs = devfdt_get_addr_ptr(dev);
+
+	gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT)
+			& pdata->pin_mask;
+
+	writel(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
+		gpio_cnt_regval | ASPEED_SGPIO_ENABLE,
+		priv->regs + ASPEED_SGPIO_CTRL);
+
+	uc_priv->gpio_count = nr_gpios * 2;
+
+	return 0;
+}
+
+static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
+	.pin_mask = GENMASK(9, 6),
+};
+
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
+	.pin_mask = GENMASK(10, 6),
+};
+
+static const struct udevice_id aspeed_sgpio_ids[] = {
+	{
+		.compatible = "aspeed,ast2400-sgpio",
+		.data = (ulong)&ast2400_sgpio_pdata
+	},
+	{
+		.compatible = "aspeed,ast2500-sgpio",
+		.data = (ulong)&ast2400_sgpio_pdata
+	},
+	{
+		.compatible = "aspeed,ast2600-sgpiom",
+		.data = (ulong)&ast2600_sgpiom_pdata
+	},
+	{}
+};
+
+U_BOOT_DRIVER(sgpio_aspeed) = {
+	.name = "sgpio_aspeed",
+	.id = UCLASS_GPIO,
+	.of_match = aspeed_sgpio_ids,
+	.ops = &sgpio_aspeed_ops,
+	.probe = aspeed_sgpio_probe,
+	.priv_auto_alloc_size = sizeof(struct aspeed_sgpio_priv),
+};
-- 
2.39.2



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