[linux dev-6.6 v1 4/6] arm64: dts: modify clock property in modules node

[Tomer Maimon]

Modify clock property handler in UART, CPU, PECI modules to reset
controller.

Signed-off-by: Tomer Maimon <tmaimon77 at gmail.com>
---
 .../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 16 ++++++++--------
 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi |  8 ++++----
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index 84a2a5172597..ed9f0edf1888 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -74,7 +74,7 @@ peci: peci-controller at 100000 {
 				compatible = "nuvoton,npcm845-peci";
 				reg = <0x100000 0x1000>;
 				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk NPCM8XX_CLK_APB3>;
+				clocks = <&rstc NPCM8XX_CLK_APB3>;
 				cmd-timeout-ms = <1000>;
 				status = "disabled";
 			};
@@ -90,7 +90,7 @@ timer0: timer at 8000 {
 			serial0: serial at 0 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x0 0x1000>;
-				clocks = <&clk NPCM8XX_CLK_UART>;
+				clocks = <&rstc NPCM8XX_CLK_UART>;
 				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				status = "disabled";
@@ -99,7 +99,7 @@ serial0: serial at 0 {
 			serial1: serial at 1000 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x1000 0x1000>;
-				clocks = <&clk NPCM8XX_CLK_UART>;
+				clocks = <&rstc NPCM8XX_CLK_UART>;
 				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				status = "disabled";
@@ -108,7 +108,7 @@ serial1: serial at 1000 {
 			serial2: serial at 2000 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x2000 0x1000>;
-				clocks = <&clk NPCM8XX_CLK_UART>;
+				clocks = <&rstc NPCM8XX_CLK_UART>;
 				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				status = "disabled";
@@ -117,7 +117,7 @@ serial2: serial at 2000 {
 			serial3: serial at 3000 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x3000 0x1000>;
-				clocks = <&clk NPCM8XX_CLK_UART>;
+				clocks = <&rstc NPCM8XX_CLK_UART>;
 				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				status = "disabled";
@@ -126,7 +126,7 @@ serial3: serial at 3000 {
 			serial4: serial at 4000 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x4000 0x1000>;
-				clocks = <&clk NPCM8XX_CLK_UART>;
+				clocks = <&rstc NPCM8XX_CLK_UART>;
 				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				status = "disabled";
@@ -135,7 +135,7 @@ serial4: serial at 4000 {
 			serial5: serial at 5000 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x5000 0x1000>;
-				clocks = <&clk NPCM8XX_CLK_UART>;
+				clocks = <&rstc NPCM8XX_CLK_UART>;
 				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				status = "disabled";
@@ -144,7 +144,7 @@ serial5: serial at 5000 {
 			serial6: serial at 6000 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x6000 0x1000>;
-				clocks = <&clk NPCM8XX_CLK_UART>;
+				clocks = <&rstc NPCM8XX_CLK_UART2>;
 				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
 				status = "disabled";
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
index 383938dcd3ce..3cbcea65eba2 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
@@ -14,7 +14,7 @@ cpus {
 		cpu0: cpu at 0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a35";
-			clocks = <&clk NPCM8XX_CLK_CPU>;
+			clocks = <&rstc NPCM8XX_CLK_CPU>;
 			reg = <0x0 0x0>;
 			next-level-cache = <&l2>;
 			enable-method = "psci";
@@ -23,7 +23,7 @@ cpu0: cpu at 0 {
 		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a35";
-			clocks = <&clk NPCM8XX_CLK_CPU>;
+			clocks = <&rstc NPCM8XX_CLK_CPU>;
 			reg = <0x0 0x1>;
 			next-level-cache = <&l2>;
 			enable-method = "psci";
@@ -32,7 +32,7 @@ cpu1: cpu at 1 {
 		cpu2: cpu at 2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a35";
-			clocks = <&clk NPCM8XX_CLK_CPU>;
+			clocks = <&rstc NPCM8XX_CLK_CPU>;
 			reg = <0x0 0x2>;
 			next-level-cache = <&l2>;
 			enable-method = "psci";
@@ -41,7 +41,7 @@ cpu2: cpu at 2 {
 		cpu3: cpu at 3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a35";
-			clocks = <&clk NPCM8XX_CLK_CPU>;
+			clocks = <&rstc NPCM8XX_CLK_CPU>;
 			reg = <0x0 0x3>;
 			next-level-cache = <&l2>;
 			enable-method = "psci";
-- 
2.34.1