[PATCH] ARM: dts: aspeed: asus: Add ASUS X4TF BMC
Kelly Hung
ppighouse at gmail.com
Tue Jan 30 20:04:47 AEDT 2024
From: kelly1732000 <Kelly_Hung at asus.com>
This initial device-tree provides the necessary configuration for
basic BMC functionality and work on ASUS X4TF production.
Signed-off-by: kelly1732000 <Kelly_Hung at asus.com>
---
.../boot/dts/aspeed/aspeed-bmc-asus-x4tf.dts | 828 ++++++++++++++++++
1 file changed, 828 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asus-x4tf.dts
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-x4tf.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-x4tf.dts
new file mode 100644
index 000000000000..723bbb33137f
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-x4tf.dts
@@ -0,0 +1,828 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2023 ASUS Corp.
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+
+/ {
+ model = "ASUS-X4TF";
+ compatible = "asus,x4tf", "aspeed,ast2600";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8 earlycon";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ video_engine_memory: video {
+ size = <0x04000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ rvas_memory: rvas {
+ size = <0x04000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ bmc_dev_memory: bmc_dev_memory {
+ size = <0x00100000>;
+ alignment = <0x00100000>;
+ compatible = "shared-dma-pool";
+ no-map;
+ };
+
+ pci_msi_memory: pci_msi_memory {
+ no-map;
+ reg = <0x9e770000 0x100>;
+ compatible = "shared-dma-pool";
+ };
+ /* 1GB memory */
+ vga_memory: region at bf000000 {
+ no-map;
+ compatible = "shared-dma-pool";
+ reg = <0xbf000000 0x01000000>; /* 16M */
+ };
+ ssp_memory: ssp_memory {
+ size = <0x02000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ no-map;
+ };
+ };
+
+ vcc_sdhci0: regulator-vcc-sdhci0 {
+ compatible = "regulator-fixed";
+ status = "disabled";
+ regulator-name = "SDHCI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhci0: regulator-vccq-sdhci0 {
+ compatible = "regulator-gpio";
+ status = "disabled";
+ regulator-name = "SDHCI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>,
+ <1800000 0>;
+ };
+
+ vcc_sdhci1: regulator-vcc-sdhci1 {
+ compatible = "regulator-fixed";
+ status = "disabled";
+ regulator-name = "SDHCI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhci1: regulator-vccq-sdhci1 {
+ compatible = "regulator-gpio";
+ status = "disabled";
+ regulator-name = "SDHCI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>,
+ <1800000 0>;
+ };
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
+ <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
+ };
+
+ video-engine at 1e700000 {
+ compatible = "aspeed,ast2600-video-engine";
+ reg = <0x1e700000 0x20000>;
+ clocks = <&syscon ASPEED_CLK_GATE_VCLK>, <&syscon ASPEED_CLK_GATE_ECLK>;
+ clock-names = "vclk", "eclk";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&video_engine_memory>;
+ //resets = <&syscon ASPEED_RESET_VIDEO>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ uid_led {
+ gpios = <&gpio0 ASPEED_GPIO(P, 1) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ default-state = "off";
+ };
+ status_Y {
+ gpios = <&gpio1 ASPEED_GPIO(B, 1) GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ sys_boot_status {
+ gpios = <&gpio1 ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+ spigpio {
+ status = "okay";
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
+ };
+
+};
+
+&adc0 {
+ vref = <2500>;
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+};
+
+&adc1 {
+ vref = <2500>;
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc10_default &pinctrl_adc11_default
+ &pinctrl_adc12_default &pinctrl_adc13_default
+ &pinctrl_adc14_default &pinctrl_adc15_default>;
+};
+
+&peci0 {
+ status = "okay";
+};
+
+&lpc_snoop {
+ snoop-ports = <0x80>;
+ status = "okay";
+};
+
+
+&mdio0 {
+ status = "disabled";
+};
+
+
+&mdio1 {
+ status = "disabled";
+};
+
+&mdio2 {
+ status = "okay";
+
+ ethphy2: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mdio3 {
+ status = "okay";
+
+ ethphy3: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mac0 {
+ status = "disabled";
+};
+
+&mac1 {
+ status = "disabled";
+};
+
+//for X4TF
+&mac2 {
+ status = "okay";
+ phy-mode = "rmii";
+ #phy-handle = <ðphy2>;
+ use-ncsi;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+};
+
+
+&mac3 {
+ status = "okay";
+ phy-mode = "rmii";
+ #phy-handle = <ðphy3>;
+ use-ncsi;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+};
+
+
+&syscon {
+ uart-clock-high-speed;
+ status = "okay";
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&fmc {
+ status = "okay";
+ flash at 0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc-spi";
+ spi-max-frequency = <50000000>;
+ spi-bus-width = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bmc at 0 {
+ label = "bmc";
+ reg = <0x0 0x4000000>;
+ };
+ u-boot at 0 {
+ label = "u-boot";
+ reg = <0x0 0x200000>;
+ };
+ u-boot-env at 1f0000 {
+ label = "u-boot-env";
+ reg = <0x1f0000 0x10000>;
+ };
+ kernel at 200000 {
+ label = "kernel";
+ reg = <0x200000 0xc00000>;
+ };
+ rofs at a00000 {
+ label = "rofs";
+ reg = <0xa00000 0x2a00000>;
+ };
+ rwfs at 2a00000 {
+ label = "rwfs";
+ reg = <0x2a00000 0x43f0000>;
+ };
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash at 0 {
+ status = "okay";
+ w25q256,fast-read;
+ label = "bios-spi";
+ spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ biosfullimg at 0 {
+ reg = <0x0 0x2000000>; // 32768 *1024 = 0x2000000, 32 MB
+ label = "biosfullimg";
+ };
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+ tmp75 at 48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+ tmp75 at 49 {
+ compatible = "ti,tmp75";
+ reg = <0x49>;
+ };
+
+ pca9555_4_20: gpio at 20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9555_4_22: gpio at 22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9555_4_24: gpio at 24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ /*A0 - A7 0*/ "", "STRAP_BMC_BATTERY_GPIO1", "", "", "", "", "", "",
+ /*B0 - B7 8*/ "", "", "", "", "", "", "", "";
+ };
+
+ pca9555_4_26: gpio at 26 {
+ compatible = "nxp,pca9555";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9546";
+ status = "okay";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel_1: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ channel_2: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ channel_3: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ channel_4: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+ pca9555_5_24: gpio at 24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9546";
+ status = "okay";
+ reg = <0x70 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel_5: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ pca9555_5_5_20: gpio at 20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ /*A0 0*/ "", "", "", "", "", "", "", "",
+ /*B0 8*/ "", "", "SYS_FAN6", "SYS_FAN5",
+ /*B4 12*/ "SYS_FAN4", "SYS_FAN3", "SYS_FAN2", "SYS_FAN1";
+ };
+ pca9555_5_5_21: gpio at 21 {
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ ina219 at 0x44 {
+ compatible = "ti,ina219";
+ reg = <0x44>;
+ rshunt = <2>;
+ };
+ };
+
+ channel_6: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ channel_7: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ channel_8: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ pca9555_6_27: gpio at 27 {
+ compatible = "nxp,pca9555";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ pca9555_6_20: gpio at 20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ /*A0 - A7 0*/ "", "", "", "", "", "", "", "",
+ /*B0 - B7 8*/ "Drive_NVMe1", "Drive_NVMe2", "", "", "", "", "", "";
+ };
+ pca9555_6_21: gpio at 21 {
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ i2c-switch at 70 {
+ compatible = "nxp,pca9546";
+ status = "okay";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ idle-state = <1>;
+
+ channel_9: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ tmp75 at 48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+ tmp75 at 49 {
+ compatible = "ti,tmp75";
+ reg = <0x49>;
+ };
+ ina219 at 0x40 {
+ compatible = "ti,ina219";
+ reg = <0x40>;
+ rshunt = <2>;
+ };
+ ina219 at 0x41 {
+ compatible = "ti,ina219";
+ reg = <0x41>;
+ rshunt = <5>;
+ };
+ };
+
+ channel_10: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ channel_11: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ channel_12: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ i2c-switch at 71 {
+ compatible = "nxp,pca9546";
+ status = "okay";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ channel_13: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ channel_14: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ channel_15: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ channel_16: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+ i2c-switch at 70 {
+ compatible = "nxp,pca9546";
+ status = "okay";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ channel_17: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ channel_18: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ tmp75 at 48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+ ina219 at 0x41 {
+ compatible = "ti,ina219";
+ reg = <0x41>;
+ rshunt = <5>;
+ };
+ };
+
+ channel_19: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ channel_20: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "disabled";
+};
+
+&i2c13 {
+ status = "disabled";
+};
+
+&i2c14 {
+ status = "okay";
+ multi-master;
+ eeprom at 50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ };
+ eeprom at 51 {
+ compatible = "atmel,24c08";
+ reg = <0x51>;
+ };
+};
+
+&sgpiom0 {
+ status = "okay";
+};
+
+&gfx {
+ pcie-reset-detect;
+ status = "disabled";
+ memory-region = <&gfx_memory>;
+};
+
+&sdc {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "disabled";
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ sdhci-drive-type = /bits/ 8 <3>;
+ /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
+ sdhci-caps-mask = <0x7 0x580000>;
+ sdhci,wp-inverted;
+};
+
+#if !defined(CONFIG_SPX_FEATURE_ENABLE_SSP)
+&sdhci1 {
+ status = "disabled";
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ sdhci-drive-type = /bits/ 8 <3>;
+ sdhci-caps-mask = <0x7 0x580000>;
+ sdhci,wp-inverted;
+};
+#endif
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+&ibt {
+ status = "disabled";
+};
+
+&kcs1 {
+ kcs_addr = <0xca0>;
+ status = "okay";
+};
+
+&kcs2 {
+ kcs_addr = <0xca8>;
+ status = "okay";
+};
+
+&kcs3 {
+ kcs_addr = <0xca2>;
+ status = "okay";
+};
+
+&kcs4 {
+ kcs_addr = <0xca4>;
+ status = "disabled";
+};
+
+&uart1 {
+ status = "disabled";
+};
+
+&uart2 {
+ status = "disabled";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+ /* GPIOB6 will be used in ASD function, do not set to be TXD4 */
+ //pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+#if defined(CONFIG_SPX_FEATURE_ENABLE_SSP)
+&uart7 {
+ status = "okay";
+};
+#endif
+
+#if defined(CONFIG_SPX_FEATURE_PLATGUARDPLUS_SUPPORT)
+&uart11 {
+ status = "okay";
+};
+#endif
+#ifdef CONFIG_SPX_FEATURE_USB_PORT_B_HOST_SUPPORT
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+#endif
+
+&vhub {
+ status = "okay";
+};
+
+#ifdef CONFIG_SPX_FEATURE_USB_PORT_B_SUPPORT
+&udc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2bd_default>;
+};
+#endif
+
+&gpio0 {
+ gpio-line-names =
+ /*A0 0*/ "", "", "", "", "", "", "", "",
+ /*B0 8*/ "", "", "", "", "", "", "PS_PWROK", "",
+ /*C0 16*/ "", "", "", "", "", "", "", "",
+ /*D0 24*/ "", "", "", "", "", "", "", "",
+ /*E0 32*/ "", "", "", "", "", "", "", "",
+ /*F0 40*/ "", "", "", "", "", "", "", "",
+ /*G0 48*/ "", "", "", "", "", "", "", "",
+ /*H0 56*/ "", "", "", "", "", "", "", "",
+ /*I0 64*/ "", "", "", "", "", "", "", "",
+ /*J0 72*/ "", "", "", "", "", "", "", "",
+ /*K0 80*/ "", "", "", "", "", "", "", "",
+ /*L0 88*/ "", "", "", "", "", "", "", "",
+ /*M0 96*/ "", "", "", "", "", "", "", "",
+ /*N0 104*/ "", "", "", "",
+ /*N4 108*/ "POST_COMPLETE", "ESR1_GPIO_AST_SPISEL", "", "",
+ /*O0 112*/ "", "", "", "", "", "", "", "",
+ /*P0 120*/ "ID_BUTTON", "ID_OUT", "POWER_BUTTON", "POWER_OUT",
+ /*P4 124*/ "RESET_BUTTON", "RESET_OUT", "", "HEARTBEAT",
+ /*Q0 128*/ "", "", "", "", "", "", "", "",
+ /*R0 136*/ "", "", "", "", "", "", "", "",
+ /*S0 144*/ "", "", "", "", "", "", "", "",
+ /*T0 152*/ "", "", "", "", "", "", "", "",
+ /*U0 160*/ "", "", "", "", "", "", "", "",
+ /*V0 168*/ "", "", "", "", "", "", "", "",
+ /*W0 176*/ "", "", "", "", "", "", "", "",
+ /*X0 184*/ "", "", "", "", "", "", "", "",
+ /*Y0 192*/ "", "", "", "", "", "", "", "",
+ /*Z0 200*/ "", "", "", "", "", "", "", "";
+};
--
2.25.1
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