[PATCH net-next 08/16] dt-bindings: net: Add Synopsys DW xPCS bindings
Serge Semin
fancer.lancer at gmail.com
Tue Dec 5 21:35:29 AEDT 2023
Synopsys DesignWare XPCS IP-core is a Physical Coding Sublayer (PCS) layer
providing an interface between the Media Access Control (MAC) and Physical
Medium Attachment Sublayer (PMA) through a Media independent interface.
>From software point of view it exposes IEEE std. Clause 45 CSR space and
can be accessible either by MDIO or MCI/APB3 bus interfaces. The later
case is described by means of a dedicated DT-bindings which imply having
the DW XPCS Management Interface defined as a DT-supernode which child the
PCSs nodes would be (in the same way as the standard MDIO buses and
devices are normally defined).
Besides of that DW XPCS DT-nodes can have the interrupts and clock source
properties specified. The former one indicates the Clause 73/37
auto-negotiation events like: negotiation page received, AN is completed
or incompatible link partner. The clock DT-properties can describe up to
two clock sources: internal one and the one connected to the chip pad.
Either of them is supposed to be used as the device reference clocks.
Finally the DW XPCS IP-core can be optionally synthesized with a
vendor-specific interface connected to Synopsys PMA (also called
DesignWare Consumer/Enterprise PHY). Alas that isn't auto-detectable
anyhow so if the DW XPCS device has the respective PMA attached then it
should be reflected in the DT-node compatible string so the driver would
be aware of the PMA-specific device capabilities (mainly connected with
CSRs available for the fine-tunings).
Signed-off-by: Serge Semin <fancer.lancer at gmail.com>
---
.../bindings/net/pcs/snps,dw-xpcs.yaml | 88 +++++++++++++++++++
.../bindings/net/snps,dw-xpcs-mi.yaml | 88 +++++++++++++++++++
2 files changed, 176 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml
create mode 100644 Documentation/devicetree/bindings/net/snps,dw-xpcs-mi.yaml
diff --git a/Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml b/Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml
new file mode 100644
index 000000000000..9694ef51abad
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare Ethernet PCS
+
+maintainers:
+ - Jose Abreu <Jose.Abreu at synopsys.com>
+
+description:
+ Synopsys DesignWare Ethernet Physical Coding Sublayer provides an interface
+ between Media Access Control and Physical Medium Attachment Sublayer through
+ the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)
+ controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
+ optionally synthesized with a vendor-specific interface connected to
+ Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
+ general it can be used to communicate with any compatible PHY.
+
+properties:
+ compatible:
+ oneOf:
+ - description: Synopsys DesignWare XPCS with none or unknown PMA
+ const: snps,dw-xpcs
+ - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
+ const: snps,dw-xpcs-gen1-3g
+ - description: Synopsys DesignWare XPCS with Consumer Gen2 3G PMA
+ const: snps,dw-xpcs-gen2-3g
+ - description: Synopsys DesignWare XPCS with Consumer Gen2 6G PMA
+ const: snps,dw-xpcs-gen2-6g
+ - description: Synopsys DesignWare XPCS with Consumer Gen4 3G PMA
+ const: snps,dw-xpcs-gen4-3g
+ - description: Synopsys DesignWare XPCS with Consumer Gen4 6G PMA
+ const: snps,dw-xpcs-gen4-6g
+ - description: Synopsys DesignWare XPCS with Consumer Gen5 10G PMA
+ const: snps,dw-xpcs-gen5-10g
+ - description: Synopsys DesignWare XPCS with Consumer Gen5 12G PMA
+ const: snps,dw-xpcs-gen5-12g
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ System interface interrupt output (sbd_intr_o) indicating Clause 73/37
+ auto-negotiation events like':' Page received, AN is completed or
+ incompatible link partner.
+ maxItems: 1
+
+ clocks:
+ description:
+ PCS/PMA interface be can clocked either by internal reference clock
+ source or by an externally connected (via a pad) clock generator.
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum: [ core, pad ]
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xgmac_pcs: ethernet-pcs at 0 {
+ compatible = "snps,dw-xpcs";
+ reg = <0>;
+
+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&ccu_core>, <&ccu_pad>;
+ clock-names = "core", "pad";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/net/snps,dw-xpcs-mi.yaml b/Documentation/devicetree/bindings/net/snps,dw-xpcs-mi.yaml
new file mode 100644
index 000000000000..67ddba9d61fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/snps,dw-xpcs-mi.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/snps,dw-xpcs-mi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare Ethernet PCS Management Interface
+
+maintainers:
+ - Serge Semin <fancer.lancer at gmail.com>
+
+description:
+ Synopsys DesignWare Ethernet PCS provides an interface between MAC and PMA
+ through the Media Independent Interface. The PCS CSRs can be accessible over
+ the Ethernet MDIO bus or directly by means of the APB3/MCI interfaces. In the
+ later case the XPCS can be mapped right to the system IO memory space.
+
+allOf:
+ - $ref: mdio.yaml#
+
+properties:
+ compatible:
+ const: snps,dw-xpcs-mi
+
+ reg:
+ items:
+ - description:
+ DW XPCS CSRs space can be either 'directly' or 'indirectly'
+ accessible. In the former case all Clause 45 registers are
+ contiguously mapped within the address space MMD '[20:16]',
+ Reg '[15:0]'. In the later case the space is divided to the
+ multiple 256 register sets. There is a special viewport CSR
+ which is responsible for the set selection. The upper part of
+ the CSR address is supposed to be written in there thus the
+ corresponding subset would be mapped over the lowest 255 CSRs.
+
+ reg-names:
+ items:
+ - enum: [ direct, indirect ]
+
+ reg-io-width:
+ description:
+ The way the CSRs are mapped to the memory is platform depended. Since
+ each Clause 45 CSR is of 16-bits wide the access instructions must be
+ two bytes aligned at least.
+ default: 2
+ enum: [ 2, 4 ]
+
+ clocks:
+ items:
+ - description: Peripheral MCI/APB3 bus clock source
+
+ clock-names:
+ items:
+ - const: pclk
+
+patternProperties:
+ 'ethernet-pcs@[0-9a-f]+$':
+ type: object
+
+ $ref: pcs/snps,dw-xpcs.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio at 1f05d000 {
+ compatible = "snps,dw-xpcs-mi";
+ reg = <0x1f05d000 0x1000>;
+ reg-names = "indirect";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clocks = <&ccu_pclk>;
+ clock-names = "pclk";
+
+ reg-io-width = <4>;
+
+ ethernet-pcs at 0 {
+ compatible = "snps,dw-xpcs";
+ reg = <0>;
+ };
+ };
--
2.42.1
More information about the openbmc
mailing list