[PATCH v6 1/3] ARM: dts: nuvoton: Add memory controller node
Paul Menzel
pmenzel at molgen.mpg.de
Sat Apr 9 15:57:39 AEST 2022
Dear Medad,
Thank you for the patch.
Am 22.03.22 um 04:01 schrieb Medad CChien:
> ECC must be configured in the BootBlock header.
bootblock
I search for *bootblock* in Linux and the git commit messages, and does
not seem to be a common term. Is that term used in the datasheet?
> Then, you can read error counts via
> the EDAC kernel framework.
Please reflow for 75 characters per line. (Also, there is no need to
break lines after a sentence, unless 75 characters are reached or a new
paragraph starts.)
Tested on what board?
> Signed-off-by: Medad CChien <ctcchien at nuvoton.com>
Out of curiosity, is the first C in CChien the letter of your middle
name, or the last name really spelled with two capital letters in the
beginning?
> ---
> arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> index 3696980a3da1..ba542b26941e 100644
> --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> @@ -106,6 +106,13 @@
> interrupt-parent = <&gic>;
> ranges;
>
> + mc: memory-controller at f0824000 {
> + compatible = "nuvoton,npcm750-memory-controller";
> + reg = <0x0 0xf0824000 0x0 0x1000>;
Is f0824000 from some datasheet?
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> rstc: rstc at f0801000 {
> compatible = "nuvoton,npcm750-reset";
> reg = <0xf0801000 0x70>;
Kind regards,
Paul
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