[PATCH dev-5.10 v5] ARM: dts: nuvoton: Add Quanta GBS BMC Device Tree

[Joel Stanley]

On Tue, 30 Mar 2021 at 07:22, George Hung <ghung.quanta at gmail.com> wrote:
>
> Add the device tree for the Quanta GBS BMC and it's
> based on NPCM730 SoC
>
> Signed-off-by: George Hung <george.hung at quantatw.com>

Thanks for the patch. I'll apply it as-is, but if you have time to
send a follow up to fix the suggestions below.

Reviewed-by: Joel Stanley <joel at jms.id.au>


> +&i2c1 {
> +       clock-frequency = <100000>;
> +       status = "okay";
> +
> +       pca9535_ifdet: pca9535-ifdet at 24 {

I think this should be:

    pca9535_ifdet: pca9535 at 24 {

The node name is the generic thing, and the phandle is the unique name
you use to refer to it. Same for all the pca9535 nodes.


> +               compatible = "nxp,pca9535";
> +               reg = <0x24>;
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +       };
> +

> +&pinctrl {
> +       pinctrl-names = "default";
> +
> +       gpio0: gpio at f0010000 {

These were missed in converting to phandle; you can pull them out to
the top level and do

&gpio0 {
 ...
}

> +               /* POWER_OUT=gpio07, RESET_OUT=gpio06, PS_PWROK=gpio13 */
> +               gpio-line-names =
> +               /*0-31*/
> +               "","","","","","","RESET_OUT","POWER_OUT",
> +               "","","","","","PS_PWROK","","",
> +               "","","","","","","","",
> +               "","","","","","","","";
> +       };

> diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> index 20e13489b993..03bb8ab8cd6c 100644
> --- a/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0
>  // Copyright (c) 2018 Nuvoton Technology tomer.maimon at nuvoton.com
>  // Copyright 2018 Google, Inc.
> +// Copyright (c) 2020 Quanta Computer Inc. George.Hung at quantatw.com
>
>  #include "nuvoton-common-npcm7xx.dtsi"
>
> @@ -44,10 +45,50 @@
>         };
>
>         ahb {
> -               udc9:udc at f0839000 {
> +               udc5: udc at f0835000 {
> +                       compatible = "nuvoton,npcm750-udc";
> +                       reg = <0xf0835000 0x1000
> +                              0xfffd2800 0x800>;
> +                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +                       status = "disabled";
> +                       clocks = <&clk NPCM7XX_CLK_SU>;
> +                       clock-names = "clk_usb_bridge";
> +               };

> +               udc8: udc at f0838000 {
> +                       compatible = "nuvoton,npcm750-udc";
> +                       reg = <0xf0838000 0x1000
> +                              0xfffd4000 0x800>;
> +                       interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> +                       status = "disabled";
> +                       clocks = <&clk NPCM7XX_CLK_SU>;
> +                       clock-names = "clk_usb_bridge";
> +               };
> +
> +               udc9: udc at f0839000 {
>                         compatible = "nuvoton,npcm750-udc";
>                         reg = <0xf0839000 0x1000
> -                              0xfffd0000 0x800>;
> +                              0xfffd4800 0x800>;

I assume this is correcting a mistake?

Cheers,

Joel