Re: [PATCH u-boot v2019.04-aspeed-openbmc v2 1/6] ast2600: Modify SPL SRAM layout

[Andrew Jeffery]

On Wed, 27 Jan 2021, at 17:30, Joel Stanley wrote:
> The SRAM is 89KB on the A1 and beyond:
> 
>  0x1000_0000 to 0x1000_ffff: 64KB, with parity check
>  0x1001_0000 to 0x1001_5fff: 24KB, w/o parity check
>  0x1001_6000 to 0x1001_63ff: 1KB, w/o parity check, each byte write once
> 
> Allow the image to fill the full 64KB payload size (max that secure boot
> supports) and place the stack at the top of the 24KB of SRAM.
> 
> Signed-off-by: Joel Stanley <joel at jms.id.au>

I've pushed a change to github that enables socsec to sign larger SPLs:

https://github.com/amboar/socsec/commit/e28d00cb8278d61b02cb65c320ab4bfa70c79ae1

Acked-by: Andrew Jeffery <andrew at aj.id.au>