Supporting new interfaces in phosphor-ipmi-flash

[Andrew Jeffery]

On Thu, 28 Jan 2021, at 17:59, Troy Lee wrote:
> Hi Andrew,
> 
> The 01/28/2021 07:14, Andrew Jeffery wrote:
> > 
> > 
> > On Wed, 27 Jan 2021, at 20:13, Troy Lee wrote:
> > > Hi team,
> > > 
> > > For security consideration, user might want to disable AST2500/AST2600 
> > > P2A functionality by default. To compensate the effect to 
> > > phosphor-ipmi-flash, we're planning to support two alternative in-band 
> > > firmware upgrade over PCIe for AST2500/AST2600 (AST2520 and AST2620 are 
> > > excluded):
> > >  - Through a reserved **VGA** memory on BAR[0], or
> > >  - Through a reserved **PCIe** shared memory on BAR[1]
> > > 
> > > The usage pretty much the same as P2A, but it runs on different BAR, 
> > > offset and length.
> > > This will involves modifying phosphor-ipmi-flash/[tools|bmc]. Should I 
> > > create new **interfaces**, e.g. astpcie/astvga?
> > > 
> > 
> > This is the HOST2BMC functionality in the 2600 datasheet?
> > 
> > It would be great to have more detail on how it works.
> > 
> > Andrew
> 
> No, it doesn't use HOST2BMC interface, it uses VGA controller's mmio.
> Perhaps HOST2BMC is also a possible solution, too.
> 
> 02:00.0 0300: 1a03:2000 (rev 51) (prog-if 00 [VGA controller])
>         Subsystem: 1a03:2000
>         Flags: bus master, medium devsel, latency 0, IRQ 16
>         Memory at f6000000 (32-bit, non-prefetchable) [size=16M]  <--- Option 1
>         Memory at f7040000 (32-bit, non-prefetchable) [size=128K] <--- Option 2
>         I/O ports at e000 [size=128]
>         Expansion ROM at 000c0000 [disabled] [size=128K]
>         Capabilities: [40] Power Management version 3
>         Capabilities: [50] MSI: Enable- Count=1/4 Maskable- 64bit+
>         Kernel driver in use: ast
>         Kernel modules: ast
> 
> Option 1 allocates a 1MB memory from the end of VGA memory, so it will
> need some change to VBIOS.
> 
> Option 2 allocates a 4K memory from BMC memory space. Since the buffer
> is smaller, the ipmi-blob protocol overhead will be greater.
> 

Okay. So for Option 2 we need to coordinate on the BMC by reserving memory in 
the devicetree. What's the plan there? Where's that going to be documented?

Andrew