[PATCH linux dev-5.8 v2] ARM: dts: aspeed: rainier: Add I2C buses for NVMe use

[Santosh Puranik]

Hi,

On 9/1/20 11:53 AM, Joel Stanley wrote:
> Hello,
>
> On Tue, 1 Sep 2020 at 06:19, Jet Li <Jet.Le at ibm.com> wrote:
>> From: Jet Li <Jet.Li at ibm.com>
>>
>> Adding pca9552 exposes the presence detect lines for the cards and
>> tca9554 exposes the presence details for the cards.

This change looks incorrect. Per the Rainier workbook,

there is no TCA chip at 0x40 on i2c0. The chip is at 0x20

and only has presence GPIOs (inputs).

Why is this using a gpio-hog to set this as an output?

--

Santosh

> This patch is already in dev-5.8 as a3ce4e380958571814bbf3e237e6496d5b35153b.
>
> Cheers,
>
> Joel
>
>> Signed-off-by: Jet Li <Jet.Li at ibm.com>
>> Signed-off-by: Joel Stanley <joel at jms.id.au>
>> ---
>>   arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 105 +++++++++++++++++++++++++++
>>   1 file changed, 105 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
>> index d20cdf3c..e803133 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
>> @@ -300,6 +300,21 @@
>>                  compatible = "atmel,24c64";
>>                  reg = <0x51>;
>>          };
>> +
>> +       tca9554 at 40 {
>> +               compatible = "ti,tca9554";
>> +               reg = <0x40>;
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               smbus0 {
>> +                       gpio-hog;
>> +                       gpios = <4 GPIO_ACTIVE_HIGH>;
>> +                       output-high;
>> +                       line-name = "smbus0";
>> +               };
>> +       };
>> +
>>   };
>>
>>   &i2c1 {
>> @@ -614,6 +629,96 @@
>>                  compatible = "atmel,24c64";
>>                  reg = <0x51>;
>>          };
>> +
>> +       pca1: pca9552 at 61 {
>> +               compatible = "nxp,pca9552";
>> +               reg = <0x61>;
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               gpio-controller;
>> +               #gpio-cells = <2>;
>> +
>> +               gpio at 0 {
>> +                       reg = <0>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 1 {
>> +                       reg = <1>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 2 {
>> +                       reg = <2>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 3 {
>> +                       reg = <3>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 4 {
>> +                       reg = <4>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 5 {
>> +                       reg = <5>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 6 {
>> +                       reg = <6>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 7 {
>> +                       reg = <7>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 8 {
>> +                       reg = <8>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 9 {
>> +                       reg = <9>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 10 {
>> +                       reg = <10>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 11 {
>> +                       reg = <11>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 12 {
>> +                       reg = <12>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 13 {
>> +                       reg = <13>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 14 {
>> +                       reg = <14>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio at 15 {
>> +                       reg = <15>;
>> +                       type = <PCA955X_TYPE_GPIO>;
>> +               };
>> +       };
>> +
>>   };
>>
>>   &i2c9 {
>> --
>> 2.7.4
>>