venture at google.com
Wed May 13 12:18:35 AEST 2020
On Tue, May 12, 2020 at 5:51 PM Benjamin Fair <benjaminfair at google.com> wrote:
> On Tue, 12 May 2020 at 17:18, Patrick Voelker
> <Patrick_Voelker at phoenix.com> wrote:
> > I got a "ipmibt" interface transfer complete and want to move on to one of the faster interfaces to speed up debug since it takes so long to transfer the FW image.
> > For the "ipmilpc" and "ipmipci" interfaces, do those options require ASPEED_LPC_CTRL and ASPEED_P2A_CTRL respectively in the BMC's kernel config? Those two configs happen to be disabled in the BMC I'm building and I've been searching for examples on how to configure the memory regions correctly both on the BMC and the host side and am not entirely sure what I'm looking for.
> Yes, you'll need the LPC or P2A drivers on the BMC to make these
> bridges work. You'll also need some extra configuration in the BIOS
> that reserves a memory region in order to use the LPC bridge.
> I believe Quanta's Q71L machine uses P2A/ipmipci for updates, so take
> a look at the device tree for an example
> (arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts). I've CC'd Patrick
> Venture, since he worked on this machine and phosphor-ipmi-flash.
> Hopefully he can fill in details if I'm missing them.
You've hit all the details for how to configure the system to use it.
You'll need to provide a configuration on the BMC-side of things on
how to handle the image update as well - for examples and an
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