回复: Regarding power control
patrick at stwcx.xyz
Tue May 5 02:00:30 AEST 2020
Can you give some suggestion on if this is something where
x86-power-control should be modified to support?
On Thu, Apr 30, 2020 at 01:58:58AM +0000, zhouyuanqing8 at outlook.com wrote:
> Hi Patrick Williams，
> My board hardware is connected to CPLD through I2C of AST2500, BMC reads and writes CPLD register through I2C, and then CPLD controls power on and off.
> So, I think The x86-power-control implementation cannot be directly adapted to my board.
> Please help me to suggest what to do next, which can solve this problem and adapt well to the code of openbmc community.
> 发件人: Patrick Williams
> 已发送: 2020 年 4 月 30 日 星期四 0:04
> 收件人: zhouyuanqing8 at outlook.com
> 抄送: openbmc; uperic at 163.com
> 主题: Re: Regarding power control
> On Wed, Apr 29, 2020 at 01:50:09PM +0000, zhouyuanqing8 at outlook.com wrote:
> > Regarding power control, I read the codes in the following two directories(github.com/openbmc/x86-power-control.git & github.com/openbmc/skeleton/tree/master/op-pwrctl). The power control is controlled by GPIO, but the power of my board is controlled by CPLD.
> The x86-power-control implementation uses GPIOs from the BMC, but those
> GPIOs are wired to a CPLD for the signalling. The CPLD monitors the
> GPIOs to know when to begin the power sequence. This is what we use on
> Patrick Williams
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 833 bytes
Desc: not available
More information about the openbmc