p2a control driver

[Patrick Venture]

On Sat, Jun 13, 2020 at 10:47 AM Montag, Gil <gil.montag at intel.com> wrote:
>
> Hi Patrick,
>
> First. Thanks for the help!
>
> 1. If I'm getting it right, it's ok that I see the ASPEED PCI-PCI bridge regardless of the configuration and I am not expected to see the PCI-AHB on lspci, one as it's not a "real" PCI bridge.
Correct.

> 2, Can you please specify which items shall I enable in the kernel config and in the dts for the aspeed-p2a-ctrl driver to be loaded properly and functional?

https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts#L115

You'll need to set aside a memory region.  The quanta-q71l has the VGA
enabled on its ast2400, but it's not configured for use, so we just
snagged that memory.  If you're using an ast2500, there is often
memory set aside for the lpc mmio region, you should be able to
leverage that.

> 3. Do you have some usage example for the code you referenced below (bmc firmware updater?)

The openbmc project has some users of this - I keep adding their
mailing list onto these emails for visibility.  I'm not sure what you
mean by examples, but, here's an example openbmc configuration for use
with phosphor-ipmi-flash:

meta-quanta-q71l/recipes-phosphor/ipmi/phosphor-ipmi-flash_%.bbappend

PACKAGECONFIG_append_quanta-q71l = " aspeed-p2a"
IPMI_FLASH_BMC_ADDRESS_quanta-q71l = "0x47FF0000"

The address specified corresponds with the device-tree entry.

>
> Thanks,
> Gil
>
>
>
> -----Original Message-----
> From: Patrick Venture <venture at google.com>
> Sent: Friday, June 12, 2020 21:58
> To: Montag, Gil <gil.montag at intel.com>
> Cc: OpenBMC Maillist <openbmc at lists.ozlabs.org>
> Subject: Re: p2a control driver
>
> On Thu, Jun 11, 2020 at 7:35 AM Montag, Gil <gil.montag at intel.com> wrote:
> >
> > Hi Patrick,
> >
> >
> >
> > I have an AST2500 BMC in my system.
> >
> > Doing lspci on the host connected to it via PCIe shows:
> >
> >
> >
> > 0e:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
> > (rev 04) (prog-if 00 [Normal decode])
> >
> >         Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> > ParErr- Stepping- SERR- FastB2B- DisINTx-
> >
> >         Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> > <TAbort- <MAbort- >SERR- <PERR- INTx-
> >
> >         Latency: 0, Cache Line Size: 64 bytes
> >
> >         Interrupt: pin A routed to IRQ 17
> >
> >         Bus: primary=0e, secondary=0f, subordinate=0f, sec-latency=32
> >
> >         I/O behind bridge: 0000e000-0000efff
> >
> >         Memory behind bridge: f6000000-f70fffff
> >
> >         Prefetchable memory behind bridge:
> > 00000000fff00000-00000000000fffff
> >
> >         Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium
> > >TAbort- <TAbort- <MAbort- <SERR- <PERR-
> >
> >         BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
> >
> >                 PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> >
> >         Capabilities: <access denied>
> >
> >
> >
> > This PCI-PCI bridge is shown regardless of the aspeed-p2a-ctrl driver loaded or not.
> >
> > Is this the bridge you refer in your patch https://patchwork.kernel.org/patch/10873949/  or should I see some downstream PCI-AHB bridge other than this one?
>
> The bridge is handled through MMIO, it's not specifically a bridge device, and the driver configures the PCI-to-AHB MMIO bridge - the PCI bridge itself exists regardless depending on the configuration.  If that makes sense.
>
> >
> > If I should see such PCI-AHB bridge, what do I need to do to really see it?
>
> The bridge is controlled from the host side with a register in BAR0, and from the BMC via the control registers.
>
> https://github.com/openbmc/phosphor-ipmi-flash/tree/master/tools <-- this handles identifying the bridge from the host-side.
>
> >
> >
> >
> > Thank you
> >
> > Gil
> >
> >
> >
> >
> >
> > ---------------------------------------------------------------------
> > Intel Israel (74) Limited
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