Re： Re： Re： How can the host access BMC's SPI Flash via LPC and How do BMC's CPU read uboot from SPI Flash when power up?

[南野ムルシエラゴ]

Hi Mr. Andrew Jeffery


Thank you for your help. Now I know how LPC2AHB bridge work. Thank you very much!


Best Regards!
Liu Hongwei




On Wed, 27 May 2020, at 22:30, 南野ムルシエラゴ wrote:
> Hi Mr. Andrew Jeffery
> 
> Thank you very much for your help. I really thanks for your 
> explanations, very detail and very clear.
> Now I am clear about the iLPC2AHB bridge. I found the iLPC2AHB bridge 
> device in AST2500, but I do not find the LPC2AHB bridge. I think maybe 
> it is integrated in LPC controller, and about how LPC2AHB work, perhaps 
> I still need some time to study this.

Right, yes, it is "hidden" in the LPC controller. You want to look at registers 
HICR7 and HICR8. Now, the descriptions for these two registers in the datasheet 
are quite cryptic. You mentioned you had found the aspeed-lpc-ctrl driver in 
the kernel earlier. This is the code that drives the LPC2AHB bridge, and it has 
the following helpful comment:

		/*
		 * The top half of HICR7 is the MSB of the BMC address of the
		 * mapping.
		 * The bottom half of HICR7 is the MSB of the HOST LPC
		 * firmware space address of the mapping.
		 *
		 * The 1 bits in the top of half of HICR8 represent the bits
		 * (in the requested address) that should be ignored and
		 * replaced with those from the top half of HICR7.
		 * The 1 bits in the bottom half of HICR8 represent the bits
		 * (in the requested address) that should be kept and pass
		 * into the BMC address space.
		 */

		/*
		 * It doesn't make sense to talk about a size or offset with
		 * low 16 bits set. Both HICR7 and HICR8 talk about the top 16
		 * bits of addresses and sizes.
		 */

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/aspeed/aspeed-lpc-ctrl.c?h=v5.7#n101

Hope that clarifies how the LPC2AHB works!

Andrew
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