MCTP over PCI on AST2500

[Michael Richardson]

Andrew Jeffery <andrew at aj.id.au> wrote:
    > On Sat, 21 Dec 2019, at 10:45, Khetan, Sharad wrote:
    >> Hi Andrew,
    >> Sorry for late response.
    >> The plan is to have MCTP in user space.
    >>

    > How are you handling this then? mmap()'ing the BAR from sysfs?

    > I plan to get back to implementing in-kernel socket-based MCTP shortly.
    > Unfortunately it slipped back a little in my priority list late last year. I'd be
    > interested in your feedback on the proposal when I get something written
    > down.

I have read through a few MCTP documents on dtmf.org, but they either dealt
with too highlevel (SMBIOS tables), or too low-level (MCTP over UART).

Is there something that I can read that explains the underlying PCI
relationships between the BMC and the host CPU's PCI/bridges?
Maybe I just need to read the AST2500 datasheet?

(I was at one point quite knowledgeable about PCI, having designed adapter
cards with multiple targets and dealt with swizzling, and BARs, etc.)

What I heard is that for typical AST2500 based BMCs, the host CPU can map the
entire address space of the AST2500, and this rather concerns me.
I had rather expected some kind of mailbox system in a specialized ram that
both systems could use to exchange data.

--
]               Never tell me the odds!                 | ipv6 mesh networks [
]   Michael Richardson, Sandelman Software Works        |    IoT architect   [
]     mcr at sandelman.ca  http://www.sandelman.ca/        |   ruby on rails    [


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