Regarding power control

Thu Apr 30 02:04:18 AEST 2020

On Wed, Apr 29, 2020 at 01:50:09PM +0000, zhouyuanqing8 at outlook.com wrote:

> Regarding power control, I read the codes in the following two directories(github.com/openbmc/x86-power-control.git & github.com/openbmc/skeleton/tree/master/op-pwrctl). The power control is controlled by GPIO, but the power of my board is controlled by CPLD. 

The x86-power-control implementation uses GPIOs from the BMC, but those
GPIOs are wired to a CPLD for the signalling.  The CPLD monitors the
GPIOs to know when to begin the power sequence.  This is what we use on
Tiogapass.

-- 
Patrick Williams
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