How can the host access BMC's SPI Flash via LPC and How do BMC's CPU read uboot from SPI Flash when power up?

[南野ムルシエラゴ]

Hi, Greetings
    A BMC usually uses aspeed's chip. To learn BMC I read the spec of aspeed's AST2500. I have long been confused by two questions when I am learning BMC.
    1. One is that: How can the host access BMC's SPI Flash via LPC? I read from AST2500's spec that the host can update the BIOS stored in the SPI flash via LPC. I also seen from AST2500's spec that the SPI controller in AST2500 can be access by host through LPC. It seems like the architecture is as below.
    Host CPU---->LPC---->SPI controller---->SPI Flash[BIOS]
    I do not know how it works, does this need to install a LPC driver in host OS and openbmc OS? And does this need software intervention?
    2. The other is that: How does BMC's CPU read uboot code from SPI flash when power up? I know that the uboot(act as bootloader) is stored in a SPI flash, and uboot is the first code that is executed by BMC's CPU. I do not know whether it is right or wrong but I think BMC's CPU can only execute the code stored in DRAM. Who copy the code from SPI flash to DRAM? Given that when BMC is powered up there is no SPI driver, how SPI controller works?
    Thanks for helping me, they really confused me for a period of time(T，T).


Best Regards!
Liu Hongwei
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ozlabs.org/pipermail/openbmc/attachments/20200424/290843e9/attachment.htm>