[PATCH linux dev-5.3 3/3] fsi: aspeed: Enable single byte FSI accesses
Andrew Jeffery
andrew at aj.id.au
Wed Oct 30 23:37:07 AEDT 2019
The OPB0 read order selection register caused a data read register value
of 0xffffffff to be read for single byte accesses over FSI. A value of
0x03 for the read order byte-access slot correctly "swaps" the BE MSB
value to the LE LSB for extraction by the APB2OPB bridge:
# devmem 0x1e79b05c
0x00030B1B
# dd if=raw bs=1 count=1 | hexdump -C
dd-588 [000] .... 15201.144814: fsi_master_read: fsi0:00:00 00000000[1]
dd-588 [000] .n.. 15201.144872: fsi_master_aspeed_opb_read: fsi: opb read: addr a0000000 size 1: result ffffffc0 status: 00000000 irq_status: 00010000
dd-588 [000] .n.. 15201.144877: fsi_master_aspeed_opb_read: fsi: opb read: addr 800000d0 size 4: result 00000000 status: 00000002 irq_status: 00010000
dd-588 [000] .n.. 15201.144880: fsi_master_aspeed_opb_read: fsi: opb read: addr 800000d0 size 4: result 00000000 status: 00000002 irq_status: 00010000
dd-588 [000] .n.. 15201.144883: fsi_master_aspeed_opb_read: fsi: opb read: addr 800001d0 size 4: result 00000000 status: 00000002 irq_status: 00010000
dd-588 [000] .n.. 15201.144885: fsi_master_aspeed_opb_error: mresp0 00000000 mstap0 00000000 mesrb0 00000000
dd-588 [000] .n.. 15201.144887: fsi_master_rw_result: fsi0:00:00 00000000[1] => {c0} ret 0
1+0 records in
1+0 records out
00000000 c0 |.|
00000001
While we're at it, clean up the half-word access read order selection in
the same manner.
Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
---
drivers/fsi/fsi-master-aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c
index 6767cd89de36..ffbfb34e82f6 100644
--- a/drivers/fsi/fsi-master-aspeed.c
+++ b/drivers/fsi/fsi-master-aspeed.c
@@ -605,7 +605,7 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)
writel(fsi_base, aspeed->base + OPB_FSI_BASE);
/* Set read data order */
- writel(0x0011bb1b, aspeed->base + OPB0_R_ENDIAN);
+ writel(0x00030b1b, aspeed->base + OPB0_R_ENDIAN);
/* Set write data order */
writel(0x0011bb1b, aspeed->base + OPB0_W_ENDIAN);
--
2.20.1
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