[RFC PATCH dev-5.1 0/6] Aspeed I2C buffer/DMA mode support
Jae Hyun Yoo
jae.hyun.yoo at linux.intel.com
Sat Jun 22 02:57:54 AEST 2019
On 6/21/2019 8:46 AM, Cédric Le Goater wrote:
> On 20/06/2019 21:49, Jae Hyun Yoo wrote:
>> This patch series adds buffer mode and DMA mode transfer support for the
>> Aspeed I2C driver. With this change, default transfer mode will be set to
>> buffer mode for better performance, and DMA mode can be selectively used
>> depends on platform configuration.
>>
>> * Buffer mode
>> AST2400:
>> It has 2 KBytes (256 Bytes x 8 pages) of I2C SRAM buffer pool from
>> 0x1e78a800 to 0x1e78afff that can be used for all busses with
>> buffer pool manipulation. To simplify implementation for supporting
>> both AST2400 and AST2500, it assigns each 128 Bytes per bus without
>> using buffer pool manipulation so total 1792 Bytes of I2C SRAM
>> buffer will be used.
>>
>> AST2500:
>> It has 16 Bytes of individual I2C SRAM buffer per each bus and its
>> range is from 0x1e78a200 to 0x1e78a2df, so it doesn't have 'buffer
>> page selection' bit field in the Function control register, and
>> neither 'base address pointer' bit field in the Pool buffer control
>> register it has. To simplify implementation for supporting both
>> AST2400 and AST2500, it writes zeros on those register bit fields
>> but it's okay because it does nothing in AST2500.
>>
>> * DMA mode
>> Only AST2500 supports DMA mode under some limitations:
>> I2C is sharing the DMA H/W with UHCI host controller and MCTP
>> controller. Since those controllers operate with DMA mode only, I2C
>> has to use buffer mode or byte mode instead if one of those
>> controllers is enabled. Also make sure that if SD/eMMC or Port80
>> snoop uses DMA mode instead of PIO or FIFO respectively, I2C can't
>> use DMA mode..
>>
>> I'm submitting this series as an RFC because it needs more test on real
>> AST2400 BMC mahines, also it needs to check if QEMU can handle this change
>> so please review and test it.
>
> QEMU should have some support for the I2C DMA mode. Lightly tested
> though. The DT would activate it, right ?
>
> C.
Hi Cédric,
Right, DMA should be enabled in dt by adding below setting into each bus
node if you are going to use I2C DMA mode.
aspeed,dma-buf-size = <4096>;
Please see an example in the 1/6 patch of this series.
Also, you should disable USB host features by disabling CONFIG_USB from
kernel configs. You could remove it from defconfig like this:
https://gerrit.openbmc-project.xyz/c/openbmc/meta-aspeed/+/22808
Or, you can simply add CONFIG_USB=n into your machine layer kernel
config overlay.
Thanks,
Jae
>> Jae Hyun Yoo (6):
>> dt-bindings: i2c: aspeed: add buffer and DMA mode transfer support
>> ARM: dts: aspeed: add I2C buffer mode support
>> irqchip/aspeed-i2c-ic: add I2C SRAM enabling control
>> i2c: aspeed: fix master pending state handling
>> i2c: aspeed: add buffer mode transfer support
>> i2c: aspeed: add DMA mode transfer support
>>
>> .../devicetree/bindings/i2c/i2c-aspeed.txt | 52 +-
>> arch/arm/boot/dts/aspeed-g4.dtsi | 42 +-
>> arch/arm/boot/dts/aspeed-g5.dtsi | 42 +-
>> drivers/i2c/busses/i2c-aspeed.c | 469 ++++++++++++++++--
>> drivers/irqchip/irq-aspeed-i2c-ic.c | 8 +
>> 5 files changed, 548 insertions(+), 65 deletions(-)
>>
>
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