[PATCH dev-5.1 v6 1/4] ARM: dts: nuvoton: Add NPCM730 common device tree include file.

[franhsutw at gmail.com]

Hi Joel,
	Thanks, I will update the new patch to fix the warning message issue soon.

Fran

> -----Original Message-----
> From: Joel Stanley <joel at jms.id.au>
> Sent: Thursday, June 6, 2019 10:05 AM
> To: Fran Hsu <franhsutw at gmail.com>
> Cc: OpenBMC Maillist <openbmc at lists.ozlabs.org>; Benjamin Fair
> <benjaminfair at google.com>; Fran Hsu <Fran.Hsu at quantatw.com>
> Subject: Re: [PATCH dev-5.1 v6 1/4] ARM: dts: nuvoton: Add NPCM730 common
> device tree include file.
> 
> Hi Fran,
> 
> On Wed, 5 Jun 2019 at 13:38, Fran Hsu <franhsutw at gmail.com> wrote:
> >
> > Quanta GSJ BMC uses the Nuvoton NPCM730 BMC soc.
> > This file describes the common setting of NPCM730 soc.
> 
> Please base your series on top of the dev-5.1 tree. The latest commit as of
> today is a17b8ac585d7faa27799f425fa4326c7a1e7ae71.
> 
> Many of the changes in this series have already bee merged.
> 
> Cheers,
> 
> Joel
> 
> >
> > Signed-off-by: Fran Hsu <Fran.Hsu at quantatw.com>
> > ---
> >  arch/arm/boot/dts/nuvoton-npcm730.dtsi | 57
> > ++++++++++++++++++++++++++
> >  1 file changed, 57 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi
> >
> > diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> > b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> > new file mode 100644
> > index 000000000000..20e13489b993
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (c) 2018 Nuvoton Technology tomer.maimon at nuvoton.com //
> > +Copyright 2018 Google, Inc.
> > +
> > +#include "nuvoton-common-npcm7xx.dtsi"
> > +
> > +/ {
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +       interrupt-parent = <&gic>;
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +               enable-method = "nuvoton,npcm750-smp";
> > +
> > +               cpu at 0 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a9";
> > +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> > +                       clock-names = "clk_cpu";
> > +                       reg = <0>;
> > +                       next-level-cache = <&l2>;
> > +               };
> > +
> > +               cpu at 1 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a9";
> > +                       clocks = <&clk NPCM7XX_CLK_CPU>;
> > +                       clock-names = "clk_cpu";
> > +                       reg = <1>;
> > +                       next-level-cache = <&l2>;
> > +               };
> > +       };
> > +
> > +       soc {
> > +               timer at 3fe600 {
> > +                       compatible = "arm,cortex-a9-twd-timer";
> > +                       reg = <0x3fe600 0x20>;
> > +                       interrupts = <GIC_PPI 13
> (GIC_CPU_MASK_SIMPLE(2) |
> > +
> IRQ_TYPE_LEVEL_HIGH)>;
> > +                       clocks = <&clk NPCM7XX_CLK_AHB>;
> > +               };
> > +       };
> > +
> > +       ahb {
> > +               udc9:udc at f0839000 {
> > +                       compatible = "nuvoton,npcm750-udc";
> > +                       reg = <0xf0839000 0x1000
> > +                              0xfffd0000 0x800>;
> > +                       interrupts = <GIC_SPI 60
> IRQ_TYPE_LEVEL_HIGH>;
> > +                       status = "disabled";
> > +                       clocks = <&clk NPCM7XX_CLK_SU>;
> > +                       clock-names = "clk_usb_bridge";
> > +               };
> > +       };
> > +};
> > --
> > 2.21.0
> >