[PATCH dev-5.1 v1 2/2] dt-binding: edac: add NPCM ECC documentation

[Joel Stanley]

Hi George,

On Thu, 23 May 2019 at 11:00, George Hung <ghung.quanta at gmail.com> wrote:
>
> From: George Hung <george.hung at quantatw.com>
>
> Add device tree documentation for Nuvoton BMC ECC
>
> Signed-off-by: George Hung <george.hung at quantatw.com>

Can you convince one of your fellow Nuvoton contributors to review this patch?

Have you submitted this patch for mainline inclusion?

> ---
>  .../bindings/edac/npcm7xx-sdram-edac.txt        | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt
>
> diff --git a/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt
> new file mode 100644
> index 000000000000..dd4dac59a5bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt
> @@ -0,0 +1,17 @@
> +Nuvoton NPCM7xx SoC EDAC device driver
> +
> +The Nuvoton NPCM7xx SoC supports DDR4 memory with/without ECC and the driver
> +uses the EDAC framework to implement the ECC detection and corrtection.
> +
> +Required properties:
> +- compatible:  should be "nuvoton,npcm7xx-sdram-edac"
> +- reg:         Memory controller register set should be <0xf0824000 0x1000>
> +- interrupts:  should be MC interrupt #25
> +
> +Example:
> +
> +       mc: memory-controller at f0824000 {
> +               compatible = "nuvoton,npcm7xx-sdram-edac";
> +               reg = <0xf0824000 0x1000>;
> +               interrupts = <0 25 4>;

I think we can use the defines for 0 and 4? GIC_SPI and IRQ_TYPE_LEVEL_HIGH.

> +       };
> --
> 2.21.0
>