[RFC v3 dev-5.2 0/5] Aspeed I2C buffer/DMA mode support

Jae Hyun Yoo jae.hyun.yoo at linux.intel.com
Fri Jul 19 05:35:15 AEST 2019

This patch series adds buffer mode and DMA mode transfer support for the
Aspeed I2C driver. With this change, default transfer mode will be set to
buffer mode for better performance, and DMA mode can be selectively used
depends on platform configuration.

* Buffer mode
    It has 2 KBytes (256 Bytes x 8 pages) of I2C SRAM buffer pool from
    0x1e78a800 to 0x1e78afff that can be used for all busses with
    buffer pool manipulation. To simplify implementation for supporting
    both AST2400 and AST2500, it assigns each 128 Bytes per bus without
    using buffer pool manipulation so total 1792 Bytes of I2C SRAM
    buffer will be used.

    It has 16 Bytes of individual I2C SRAM buffer per each bus and its
    range is from 0x1e78a200 to 0x1e78a2df, so it doesn't have 'buffer
    page selection' bit field in the Function control register, and
    neither 'base address pointer' bit field in the Pool buffer control
    register it has. To simplify implementation for supporting both
    AST2400 and AST2500, it writes zeros on those register bit fields
    but it's okay because it does nothing in AST2500.

* DMA mode
  Only AST2500 supports DMA mode under some limitations:
    I2C is sharing the DMA H/W with UHCI host controller and MCTP
    controller. Since those controllers operate with DMA mode only, I2C
    has to use buffer mode or byte mode instead if one of those
    controllers is enabled. Also make sure that if SD/eMMC or Port80
    snoop uses DMA mode instead of PIO or FIFO respectively, I2C can't
    use DMA mode.

I'm submitting this series as an RFC because it needs more test on real
AST2400 BMC machines, also it needs to check if QEMU can handle this change
so please review and test it.


Changes since v2:
 - Removed 'reg-names' from device tree to make driver compatible with old
   device tree.
 - Fixed resource getting logic using indices instead of reg-names to make
   this driver compatible with old device trees.
 - Refined slave RX flow to get rid of duplicate read on the first byte of
   received data.

Changes since v1:
- Moved I2C SRAM enabling code from irq-aspeed-i2c-ic module to i2c-aspeed
- Added I2C global register node in device tree.
- Fixed DMA buffer size in dt from 4096 to 4095 which H/W actually supports.

Jae Hyun Yoo (5):
  dt-bindings: i2c: aspeed: add buffer and DMA mode transfer support
  ARM: dts: aspeed: add I2C buffer mode support
  i2c: aspeed: fix master pending state handling
  i2c: aspeed: add buffer mode transfer support
  i2c: aspeed: add DMA mode transfer support

 .../devicetree/bindings/i2c/i2c-aspeed.txt    |  65 ++-
 arch/arm/boot/dts/aspeed-g4.dtsi              |  47 +-
 arch/arm/boot/dts/aspeed-g5.dtsi              |  47 +-
 drivers/i2c/busses/i2c-aspeed.c               | 510 ++++++++++++++++--
 4 files changed, 583 insertions(+), 86 deletions(-)


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