phosphor-ipmi-flash: A problem in BMC FW update over LPC

[Corey Chen (陳志銘)]

Hi,

Currently, I’m doing following steps,

  1. Get a MMIO space via GCD service.
  2. Program LPC/eSPI PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address.
  3. Program LPC/eSPI PCI Offset 98h [31:16, 0] to [Address, 1].
  4. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h.

But after discussing with Intel,
perhaps I have to make sure that the MMIO space I’m using is claimed in MMIO_RULE_CFG_X as Skylake BIOS writer guide mentions.

BR,
Corey

From: CS20 KWLiu [mailto:KWLIU at nuvoton.com]
Sent: Friday, August 23, 2019 7:13 PM
To: Patrick Venture <venture at google.com>
Cc: CS20 CTCchien <CTCCHIEN at nuvoton.com>; Corey Chen (陳志銘) <Corey.Chen at quantatw.com>; Fran Hsu (徐誌謙) <Fran.Hsu at quantatw.com>; Samuel Jiang (江騏先) <Samuel.Jiang at quantatw.com>; George Hung (洪忠敬) <George.Hung at quantatw.com>; openbmc at lists.ozlabs.org
Subject: phosphor-ipmi-flash: A problem in BMC FW update over LPC

Hello Patrick:

We are currently trying to enable the BMC FW update over LPC on our platform (nuvoton BMC), but we encounter a problem with BIOS.

The BIOS engineer has reserved memory region as mmio space, but we couldn't see any data change in this region during run burn_my_bmc.

We have checked the BMC setting(in lpc_nuvoton.c and LDN SHM) but we couldn't identify the root cause of this problem.

Is there any settings we lost?

Thanks,
Joseph
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