[PATCH dev-5.0] ARM: dts: aspeed: zaius: add Infineon and Intersil regulators
Patrick Venture
venture at google.com
Fri Apr 19 00:14:15 AEST 2019
On Wed, Apr 17, 2019 at 11:17 PM Andrew Jeffery <andrew at aj.id.au> wrote:
>
>
>
> On Wed, 17 Apr 2019, at 01:00, Patrick Venture wrote:
> > On Fri, Apr 12, 2019 at 7:42 AM Patrick Venture <venture at google.com> wrote:
> > >
> > > From: Maxim Sloyko <maxims at google.com>
> > >
> > > Add the nodes for the ir38064 and isl68137 devices on the Zaius board.
> > >
> > > Signed-off-by: Maxim Sloyko <maxims at google.com>
> > > Signed-off-by: Robert Lippert <rlippert at google.com>
> > > Signed-off-by: Patrick Venture <venture at google.com>
> > > ---
> > > arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 65 ++++++++++++++++++++--
> > > 1 file changed, 60 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> > > index 0c0ea41cbe27..53751adebf17 100644
> > > --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> > > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
> > > @@ -301,6 +301,32 @@
> > > reg = <0x54>;
> > > };
> > > };
> > > +
> > > + };
> > > +
> > > + vrm at 64 {
> > > + compatible = "intersil,isl68137";
> > s/intersil/isil/g
>
> Hrm, I didn't see this follow up and applied the patch as is.
>
> Can you send a fix-up if necessary?
Yeah, I can send a fixup. The fixed up patch was sent out for review
to Joel's staging repo the other day. In this case, should I send a
fixup here or just wait until this patchset is dropped when the next
rebase occurs?
>
> Andrew
>
> >
> > > + reg = <0x64>;
> > > + };
> > > +
> > > + vrm at 40 {
> > > + compatible = "intersil,isl68137";
> > > + reg = <0x40>;
> > > + };
> > > +
> > > + vrm at 60 {
> > > + compatible = "intersil,isl68137";
> > > + reg = <0x60>;
> > > + };
> > > +
> > > + vrm at 43 {
> > > + compatible = "infineon,ir38064";
> > > + reg = <0x43>;
> > > + };
> > > +
> > > + vrm at 41 {
> > > + compatible = "intersil,isl68137";
> > > + reg = <0x41>;
> > > };
> > >
> > > /* Master selector PCA9541A @70h (other master: CPU0)
> > > @@ -316,18 +342,47 @@
> > > /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
> > > /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
> > > /* CPU0 VR ISL68137 0.8V PMBUS @60h */
> > > - /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
> > > + /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */
> > > /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
> > > + /* Master selector PCA9541A @70h (other master: CPU0)
> > > + * LM5066I PMBUS @10h
> > > + */
> > > + /* 12V SMPS Q54SH12050NNDH @61h */
> > > };
> > >
> > > &i2c8 {
> > > status = "okay";
> > >
> > > - /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
> > > - /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
> > > - /* CPU1 VR ISL68137 0.8V PMBUS @61h */
> > > + vrm at 64 {
> > > + compatible = "intersil,isl68137";
> > > + reg = <0x64>;
> > > + };
> > > +
> > > + vrm at 40 {
> > > + compatible = "intersil,isl68137";
> > > + reg = <0x40>;
> > > + };
> > > +
> > > + vrm at 41 {
> > > + compatible = "intersil,isl68137";
> > > + reg = <0x41>;
> > > + };
> > > +
> > > + vrm at 42 {
> > > + compatible = "infineon,ir38064";
> > > + reg = <0x42>;
> > > + };
> > > +
> > > + vrm at 60 {
> > > + compatible = "intersil,isl68137";
> > > + reg = <0x60>;
> > > + };
> > > +
> > > + /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */
> > > + /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */
> > > + /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */
> > > /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
> > > - /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
> > > + /* CPU1 VR ISL68137 0.8V PMBUS @60h */
> > > };
> > >
> > >
> > > --
> > > 2.21.0.392.gf8f6787159e-goog
> > >
> >
More information about the openbmc
mailing list