[PATCH linux dev-4.13] fsi/fsi-master-gpio: Delay sampling of FSI data input

[Christopher Bostic]

Reviewed-by: Christopher Bostic <cbostic at linux.vnet.ibm.com>


On 5/15/18 8:05 AM, Benjamin Herrenschmidt wrote:
> Most SoC GPIO implementations, including the Aspeed one, have
> synchronizers on the GPIO inputs. This means that the value
> read from a GPIO is a couple of clocks old, from whatever clock
> source feeds those synchronizers.
>
> In practice, this means that in no-delay mode, we are using a
> value that can potentially be a bit too old and too close to
> the clock edge establishing the data on the other side of the link.
>
> The voltage converters we use on some systems make this worse
> and sensitive to things like voltage fluctuations etc... This is,
> we believe, the cause of occasional CRC errors encountered during
> heavy activity on the LPC bus.
>
> This is fixed by introducing a dummy GPIO read before the actual
> data read. It slows down SBEFIFO by about 15% (less than any delay
> primitive) and the end result is so far solid.
>
> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> ---
>   drivers/fsi/fsi-master-gpio.c | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c
> index 98700eac16fd..36a71efd802c 100644
> --- a/drivers/fsi/fsi-master-gpio.c
> +++ b/drivers/fsi/fsi-master-gpio.c
> @@ -98,6 +98,11 @@ static int sda_clock_in(struct fsi_master_gpio *master)
>   	if (!master->no_delays)
>   		ndelay(FSI_GPIO_STD_DLY);
>   	gpiod_set_value(master->gpio_clk, 0);
> +
> +	/* Dummy read to feed the synchronizers */
> +	gpiod_get_value(master->gpio_data);
> +
> +	/* Actual data read */
>   	in = gpiod_get_value(master->gpio_data);
>   	if (!master->no_delays)
>   		ndelay(FSI_GPIO_STD_DLY);
>