[PATCH linux dev-4.13] clk: aspeed: Mark bclk (PCIe) as critical

Lei YU mine260309 at gmail.com
Tue Mar 27 18:52:17 AEDT 2018


Tested-by: Lei YU <mine260309 at gmail.com>

With the patch, bclk is enabled (by default).
However, the PCI/VGA device is probed by skiboot but failed to train
in petiboot:

[   55.446446203,5] PHB#0005:02:00.0 [PCID] 1a03 2000 R:41 C:030000 (
         vga)
...
[   72.096462749,3] PHB#0005[0:5]: PHB Freeze/Fence detected !
...

The full log is posted at
https://github.com/openbmc/openbmc/files/1850909/log_romulus_host_with_bmc_4.13.txt

On Mon, Mar 26, 2018 at 4:07 PM, Andrew Jeffery <andrew at aj.id.au> wrote:
> On Mon, 26 Mar 2018, at 15:46, Joel Stanley wrote:
>> This is used by the host to talk to the BMC's PCIe slave device. The BMC
>> is not involved, but the clock needs to be enabled so the host can use
>> the device.
>>
>> Signed-off-by: Joel Stanley <joel at jms.id.au>
>
> Acked-by: Andrew Jeffery <andrew at aj.id.au>
>
>> ---
>>  drivers/clk/clk-aspeed.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
>> index 5af80b4e673e..5be88f0a0678 100644
>> --- a/drivers/clk/clk-aspeed.c
>> +++ b/drivers/clk/clk-aspeed.c
>> @@ -97,7 +97,7 @@ static const struct aspeed_gate_data aspeed_gates[] =
>> {
>>       [ASPEED_CLK_GATE_GCLK] =        {  1,  7, "gclk-gate",          NULL,   0 }, /* 2D engine */
>>       [ASPEED_CLK_GATE_MCLK] =        {  2, -1, "mclk-gate",          "mpll",
>> CLK_IS_CRITICAL }, /* SDRAM */
>>       [ASPEED_CLK_GATE_VCLK] =        {  3,  6, "vclk-gate",          NULL,   0 }, /* Video
>> Capture */
>> -     [ASPEED_CLK_GATE_BCLK] =        {  4, 10, "bclk-gate",          "bclk", 0 }, /* PCIe/PCI
>> */
>> +     [ASPEED_CLK_GATE_BCLK] =        {  4, 10, "bclk-gate",          "bclk",
>> CLK_IS_CRITICAL }, /* PCIe/PCI */
>>       [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",          NULL,   0 }, /* DAC */
>>       [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",        "clkin",
>> CLK_IS_CRITICAL },
>>       [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3, "usb-port2-gate",     NULL,   0 }, /*
>> USB2.0 Host port 2 */
>> --
>> 2.15.1
>>


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