[PATCH linux dev-4.10] ARM: dts: aspeed: Add Portwell Neptune machine

[Joel Stanley]

On Fri, Mar 9, 2018 at 11:51 AM, Amithash Prasad <amithash at fb.com> wrote:
> Initial introduction of Portwell Neptune family equipped with
> Aspeed 2500 BMC SoC. This adds the neptune platform device tree
> file including the flash layout used by the neptune machines.

I like to have a sentence about the machine it's in. Something like:

Neptune is a x86 server development kit with a ASPEED ast2500 BMC
manufactured by Portwell.

Or whatever you think sounds good :)

The device tree looks good; I've made a few comments below and I've
cc'd Andrew to get a review of the pinctrl parts.

>
> Signed-off-by: Amithash Prasad <amithash at fb.com>
> ---
>  .../devicetree/bindings/vendor-prefixes.txt        |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts  | 145 +++++++++++++++++++++
>  3 files changed, 147 insertions(+)
>  create mode 100644 arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 84601d8..9dbbe7d 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -228,6 +228,7 @@ pine64      Pine64
>  pixcir  PIXCIR MICROELECTRONICS Co., Ltd
>  plathome       Plat'Home Co., Ltd.
>  plda   PLDA
> +portwell       Portwell Inc.
>  powervr        PowerVR (deprecated, use img)
>  pulsedlight    PulsedLight, Inc
>  qca    Qualcomm Atheros, Inc.
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 7c54fc8..044b960 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -993,6 +993,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
>         aspeed-bmc-mellanox-msn.dtb \
>         aspeed-bmc-quanta-q71l.dtb \
>         aspeed-bmc-intel-s2600wf.dtb \
> +       aspeed-bmc-portwell-neptune.dtb \
>         aspeed-ast2500-evb.dtb
>  endif
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
> new file mode 100644
> index 0000000..542a4cad
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
> @@ -0,0 +1,145 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2017 Facebook Inc.
> +/dts-v1/;
> +
> +#include "aspeed-g5.dtsi"
> +#include <dt-bindings/gpio/aspeed-gpio.h>
> +
> +/ {
> +       model = "Portwell Neptune BMC";
> +       compatible = "portwell,neptune-bmc", "aspeed,ast2500";
> +       aliases {
> +               serial0 = &uart1;
> +               serial4 = &uart5;
> +       };
> +       chosen {
> +               stdout-path = &uart5;
> +               bootargs = "console=ttyS4,115200 earlyprintk";
> +       };
> +
> +       memory {
> +               reg = <0x80000000 0x20000000>;
> +       };
> +
> +       leds {
> +               compatible = "gpio-leds";
> +               postcode0 {
> +                       label="BMC_UP";
> +                       gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
> +                       default-state = "on";
> +               };
> +               postcode1 {
> +                       label="BMC_HB";
> +                       gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
> +                       linux,default-trigger = "heartbeat";
> +               };
> +               postcode2 {
> +                       label="FAULT";
> +                       gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
> +               };
> +               // postcode3-7 are GPIOH3-H7
> +       };
> +};
> +
> +&wdt2 {
> +       status = "okay";
> +};

We can drop this; the upstream dts now enables wdt1 and wdt2 by default.

> +
> +&fmc {
> +       status = "okay";
> +       flash at 0 {
> +               status = "okay";
> +               m25p,fast-read;
> +#include "openbmc-flash-layout.dtsi"
> +       };
> +};
> +
> +&spi1 {
> +       status = "okay";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_spi1_default>;
> +       flash at 0 {
> +               status = "okay";
> +               m25p,fast-read;
> +               label = "pnor";
> +       };
> +};
> +
> +&uart1 {
> +       // Host Console
> +       status = "okay";

I think you need the pinctrl nodes for this. Andrew J can provide more detail.

> +};
> +
> +&uart5 {
> +       // BMC Console
> +       status = "okay";
> +};
> +
> +&mac0 {
> +       status = "okay";
> +
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_rmii1_default>;
> +       use-ncsi;
> +};
> +
> +&i2c3 {
> +       status = "okay";
> +       // SMBus to COMe AB
> +};
> +
> +&i2c4 {
> +       status = "okay";
> +       // I2C to COMe AB
> +};
> +
> +&i2c5 {
> +       status = "okay";
> +       pca9555 at 4e {
> +               compatible = "nxp,pca9555";
> +               pinctrl-names = "default";
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               reg = <0x27>;
> +       };
> +};
> +
> +&i2c6 {
> +       status = "okay";
> +       tpm at 20 {
> +               compatible = "infineon,slb9645tt";
> +               reg = <0x20>;
> +       };
> +       tmp421 at 9c {
> +               compatible = "ti,tmp421";
> +               reg = <0x4e>;
> +       };
> +       tmp421 at 9e {
> +               compatible = "ti,tmp421";
> +               reg = <0x4f>;
> +       };
> +};
> +
> +&i2c8 {
> +       status = "okay";
> +       eeprom at a2 {
> +               compatible = "atmel,24c128";
> +               reg = <0x51>;
> +               pagesize = <0x32>;
> +       };
> +};
> +
> +&pwm_tacho {
> +       status = "okay";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
> +       fan at 0 {
> +               reg = <0x00>;
> +               aspeed,fan-tach-ch = /bits/ 8 <0x00>;
> +       };
> +
> +       fan at 1 {
> +               reg = <0x01>;
> +               aspeed,fan-tach-ch = /bits/ 8 <0x01>;
> +       };
> +};
> --
> 2.9.5
>