[PATCH v1 0/1] arm: npcm: enable L2 cache in NPCM7xx architecture
tmaimon77 at gmail.com
Thu Apr 12 08:01:09 AEST 2018
On 10 April 2018 at 17:41, Arnd Bergmann <arnd at arndb.de> wrote:
> On Sun, Apr 8, 2018 at 4:03 PM, Tomer Maimon <tmaimon77 at gmail.com> wrote:
> > This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC
> > by adding L2 cache parameters into NPCM7xx DT machine start structure.
> > At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments
> > regarding the flags use in L2 cache module.
> > - https://www.spinics.net/lists/arm-kernel/msg613212.html
> > After checking again the L2 cache use in the NPCM7xx,
> > the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE
> > and it is done in the device tree:
> > https://patchwork.kernel.org/patch/10063497/
> > L2 cache flag mask allowed all the flag option.
> I've applied the patch to my fixes branch now, but took your description
> instead of the two-line text that you had in the patch itself. I liked
> the longer
> text much better.
Thanks a lot!
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