[PATCH linux dev-4.10] ARM: aspeed: romulus: Add reset tolerance for power GPIOs
Lei YU
mine260309 at gmail.com
Tue Oct 31 12:43:36 AEDT 2017
On Tue, Oct 31, 2017 at 7:58 AM, Andrew Jeffery <andrew at aj.id.au> wrote:
> On Mon, 2017-10-30 at 17:20 +0800, Lei YU wrote:
>> This is a similar change as Witherspoon, that enables the host to stay
>> up across BMC reboots.
>>
>> Signed-off-by: Lei YU <mine260309 at gmail.com>
>> ---
>> arch/arm/mach-aspeed/aspeed.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
>> index c84c871..5965bbf 100644
>> --- a/arch/arm/mach-aspeed/aspeed.c
>> +++ b/arch/arm/mach-aspeed/aspeed.c
>> @@ -196,7 +196,17 @@ static void __init do_witherspoon_setup(void)
>>
>> static void __init do_romulus_setup(void)
>> {
>> + unsigned long reg;
>> +
>> do_common_setup();
>> +
>> + /* Reset tolerance for BMC_POWER_UP (GPIOD1) */
>> + reg = readl(AST_IO(AST_BASE_GPIO | 0x01c));
>> + writel(reg | BIT(25), AST_IO(AST_BASE_GPIO | 0x01c));
>> +
>> + /* Reset tolerance for SOFTWARE_PGOOD (GPIOR1) and SEQ_CONT (GPIOS7) */
>
> What is SEQ_CONT? I'd guess at "power sequence continue". GPIOS7 doesn't have
> an associated net name in the schematic I have for Romulus, though it's pulled
> up to 3.3V. Maybe my schematic is out of date?
Exactly, it is "power sequence continue" that Romulus CPLD handles this:
* When it's high, CPLD pauses power sequence and when it's low it
continue the sequence.
This behavior is used for vcs workaround for DD1.x
* When system is powered on it shall be low, and if it becomes high,
CPLD results in PGOOD fault.
Pass1 schematic does not have this and it's done by Nick's EC;
Pass2 schematic has this GPIO named SEQ_CONT.
Thanks.
>
> Cheers,
>
> Andrew
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