OpenBMC community telecon - 11/20 Agenda
ed.tanous at intel.com
Tue Nov 21 06:57:12 AEDT 2017
Please rename/append to code review velocity: master branch stability (assuming it was my topic from email last week)
Also, please add:
I'd like to have a discussion around our desires for runtime configurability and runtime data-driven platform configurations. This includes runtime configurable sensors, platform hardware configuration changes, and Chassis detection. I'd like to have a short rundown of how we've handled these things in past codebases, and see if there's any alignment with other community needs.
Secure coding guidelines:
What secure coding guidelines are other groups/individuals using? I'd like to have an open discussion about how to move toward more secure coding guidelines with the minimum possible interruption while alienating the minimum number of people. Some subtopics:
1. Can anything be enforced at the master branch?
2. Can anything be enforced by policy? (example: reference components must be secure)
3. Does anyone have experience with automating secure coding guidelines?
(to be clear, by secure coding guidelines I mean range checked buffer interfaces, not using memory unsafe functions, exception safe code, anti stack smashing compiler flags, ect)
> -----Original Message-----
> From: openbmc [mailto:openbmc-
> bounces+ed.tanous=intel.com at lists.ozlabs.org] On Behalf Of Brad Bishop
> Sent: Monday, November 20, 2017 11:27 AM
> To: OpenBMC Maillist <openbmc at lists.ozlabs.org>
> Subject: OpenBMC community telecon - 11/20 Agenda
> IBM testing overview
> Code review velocity
> Open Mic
> Monday, 10:00pm EDT
> password: 85891389
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