[PATCH linux dev-4.10 v4] ARM: aspeed: Add Mellanox MSN machine (aspeed arch)

[Joel Stanley]

On Tue, May 30, 2017 at 10:08 PM, Mykola Kostenok
<c_mykolak at mellanox.com> wrote:
> Initial introduction of Mellanox switches of MSNXXXX family equipped
> with Aspeed 2520 BMC SoC. This adds the platform early initialization.
>
> Signed-off-by: Mykola Kostenok <c_mykolak at mellanox.com>

Thanks, applied to dev-4.10.

Please follow up with the RMII clock and MAC strapping issues - these
should be fixed by correcting the hardware strapping. We would prefer
not to have a workaround in the kernel tree.

Cheers,

Joel

> ---
> v1->v2
> Fixed issues pointed out by Joel:
> - Make commit title shorter.
> - Replace flash layout from separate dtsi to dts.
> - Change compatible = "mellanox,msnxxxx-bmc" to "mellanox,msn-bmc".
> - Remove no-hw-checksum from dts.
> - Add comments.
> - Remove WD2 disable from aspeed.c
> - Add wdt2 to dts.
>
> v2->v3
> - Split v2 patch into three separate.
>
> v3->v4
> Fixed issues pointed by Andrew:
> - Fix comment.
> - Fix UART1 reset disable sequence(read/modify/write).
> ---
>  arch/arm/mach-aspeed/aspeed.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> index 0f1a536ba1b2..5c88286c96fd 100644
> --- a/arch/arm/mach-aspeed/aspeed.c
> +++ b/arch/arm/mach-aspeed/aspeed.c
> @@ -188,6 +188,31 @@ static void __init do_lanyang_setup(void)
>         writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
>  }
>
> +static void __init do_mellanox_setup(void)
> +{
> +       unsigned long reg;
> +
> +       do_common_setup();
> +
> +       /* Set strapping for MAC1 to RMII/NCSI and MAC2 to RGMII. */
> +       reg = readl(AST_IO(AST_BASE_SCU | 0x70));
> +       reg |= BIT(7);
> +       reg &= ~BIT(6);
> +       writel(reg, AST_IO(AST_BASE_SCU | 0x70));
> +
> +       /* Disable default behavior of UART1 being held in reset by LPCRST#.
> +        * By releasing UART1 from being controlled by LPC reset, it becomes
> +        * immediately available regardless of the host being up. */
> +       reg = readl(AST_IO(AST_BASE_LPC | 0x98));
> +       /* Clear "Enable UART1 reset source from LPC" */
> +       writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
> +
> +       /* Enable RMII1 50MHz RCLK output. */
> +       reg = readl(AST_IO(AST_BASE_SCU | 0x48));
> +       reg |= BIT(29);
> +       writel(reg, AST_IO(AST_BASE_SCU | 0x48));
> +}
> +
>  #define SCU_PASSWORD   0x1688A8A8
>
>  static void __init aspeed_init_early(void)
> @@ -227,6 +252,8 @@ static void __init aspeed_init_early(void)
>                 do_romulus_setup();
>         if (of_machine_is_compatible("inventec,lanyang-bmc"))
>                 do_lanyang_setup();
> +       if (of_machine_is_compatible("mellanox,msn-bmc"))
> +               do_mellanox_setup();
>  }
>
>  static void __init aspeed_map_io(void)
> --
> 2.11.0
>