[PATCH linux dev-4.7 2/2] arm: aspeed: romulus: Disable LPC reset for UART1

[Joel Stanley]

On Thu, Mar 23, 2017 at 5:14 PM, Lei YU <mine260309 at gmail.com> wrote:
> This follows Zaius's fix, that clear the LPC block control bit that
> enables LPCRST# as a reset source for UART1, making UART1
> immediately useful in that it won't discard bytes.
>
> Signed-off-by: Lei YU <mine260309 at gmail.com>

It's not ideal to be adding more hacks to the board file. We need to
add a driver for doing this reset.

I have applied the patch to dev-4.7 so your system can work now.

Cheers,

Joel

> ---
>  arch/arm/mach-aspeed/aspeed.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> index 7ac006a..a7b03a0 100644
> --- a/arch/arm/mach-aspeed/aspeed.c
> +++ b/arch/arm/mach-aspeed/aspeed.c
> @@ -220,6 +220,7 @@ static void __init do_witherspoon_setup(void)
>
>  static void __init do_romulus_setup(void)
>  {
> +       unsigned long reg;
>         do_common_setup();
>
>         /* Set SPI1 CE1 decoding window to 0x34000000 */
> @@ -227,6 +228,14 @@ static void __init do_romulus_setup(void)
>
>         /* Set SPI1 CE0 decoding window to 0x30000000 */
>         writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));
> +
> +    /* Disable default behavior of UART1 being held in reset by LPCRST#.
> +     * By releasing UART1 from being controlled by LPC reset, it becomes
> +     * immediately available regardless of the host being up.
> +     */
> +    reg = readl(AST_IO(AST_BASE_LPC | 0x98));
> +    /* Clear "Enable UART1 reset source from LPC" */
> +    writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
>  }
>
>  #define SCU_PASSWORD   0x1688A8A8
> --
> 1.9.1
>