[PATCH linux dev-4.10] ARM: aspeed: fix reset of AHB controller

Joel Stanley joel at jms.id.au
Thu Jun 22 15:13:21 AEST 2017

We have a reset of the AHB controller in the early boot path otherwise
some peripherals (i2c) are not accessible.

The reset register is level triggered (for all lines except the JTAG
peripheral): write 1 to reset, write 0 has no effect.

In c93456b24c68 ("aspeed: Don't blast SCU04 at boot time") we tried to
preserve the state of the JTAG controller, however, we inadvertently
reset a bunch of devices by doing the read/modify/write to the reset

Preserve only the state of the JTAG reset.

Fixes: c93456b24c68 ("aspeed: Don't blast SCU04 at boot time")
Signed-off-by: Joel Stanley <joel at jms.id.au>
Tested that i2c works again on the evb

 arch/arm/mach-aspeed/aspeed.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 4c5c4853e778..32eb36183e92 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -237,12 +237,14 @@ static void __init do_mellanox_setup(void)
 static void __init aspeed_init_early(void)
+	u32 reg;
 	/* Unlock SCU */
-	/* Reset AHB bridges */
-	writel(readl(AST_IO(AST_BASE_SCU | 0x04)) | 0x02,
-	       AST_IO(AST_BASE_SCU | 0x04));
+	/* Reset AHB bridges. Do not modify the JTAG configuration bit */
+	reg = readl(AST_IO(AST_BASE_SCU | 0x04)) & BIT(22);
+	writel(reg | 0x02, AST_IO(AST_BASE_SCU | 0x04));
 	/* Enables all the clocks except D2CLK, USB1.1 Host, USB1.1, LHCLK */
 	writel(0x10CC5E80, AST_IO(AST_BASE_SCU | 0x0c));

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