[PATCH linux dev-4.10] ARM: aspeed: Request WDTRST1 pinctrl function

Andrew Jeffery andrew at aj.id.au
Wed Jul 26 16:26:30 AEST 2017

On Witherspoon, the Aspeed SoC's WDTRST1 pin is wired to the FAULT pin
on the MAX31785 fan controller, which drives the fans to 100% PWM duty
when asserted. The pulse generated by the watchdog is latched to ensure
the fans stay at full speed across the BMC reboot. The latch is reset
when the BMC transitions through the chassis-poweron systemd target.

The SoC's WDTRST1 pinctrl function needs to be requested for
aspeed,external-signal to be effective, otherwise the pin is not
associated with the watchdog controller.

Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
Cc: Matt Spinler <mspinler at linux.vnet.ibm.com>
I gave this a quick spin under QEMU to verify the right SCU bits were set. That
seems to be the case.

Matt: Can you please give it a try and reply with a Tested-by tag?

 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index d9649013ee78..c28222c17d03 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -488,6 +488,9 @@
 &wdt1 {
 	aspeed,reset-type = "none";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdtrst1_default>;
 &wdt2 {

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