[PATCH v2 1/3] ARM: dts: aspeed-g5: Add mailbox and LPC control node

[Cyril Bur]

Both these devices exist on the LPC bus these nodes are children of a
new LPC bus node.

Signed-off-by: Cyril Bur <cyrilbur at gmail.com>
---
v2:
	Add the core to to the dtsi
	Enable them in the platforms that want them in subsequent patches
	Remove the compatible property for the reserved-memory nodes
	  All my understanding seems to indicate that this is how it
	  should be. However i've had problems with drivers probing on
	  other systems, hopefully these problems will turn out to have
	  been unrelated.

 arch/arm/boot/dts/aspeed-g5.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d6ff41ee6c58..1ce07d0ed431 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -89,6 +89,44 @@
 			};
 		};
 
+		lpc: lpc at 1e789000 {
+			compatible = "aspeed,ast2500-lpc", "simple-mfd";
+			reg = <0x1e789000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x1e789000 0x1000>;
+
+			lpc_bmc: lpc-bmc at 0 {
+				compatible = "aspeed,ast2500-lpc-bmc";
+				reg = <0x0 0x80>;
+			};
+
+			lpc_host: lpc-host at 80 {
+				compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+				reg = <0x80 0x1e0>;
+				reg-io-width = <4>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x80 0x1e0>;
+
+				lpc_ctrl: lpc-ctrl at 0 {
+					compatible = "aspeed,ast2500-lpc-ctrl";
+					reg = <0x0 0x80>;
+					status = "disabled"
+				};
+
+				mbox: mbox at 180 {
+					compatible = "aspeed,ast2500-mbox";
+					reg = <0x180 0x5c>;
+					interrupts = <46>;
+					#mbox-cells = <1>;
+					status = "disabled"
+				};
+			};
+		};
+
 		vic: interrupt-controller at 1e6c0080 {
 			compatible = "aspeed,ast2400-vic";
 			interrupt-controller;
-- 
2.11.0