[PATCH linux v2 0/3] ASPEED SPI driver support for dual IO mode

Rob Lippert roblip at gmail.com
Sat Jan 14 11:03:18 AEDT 2017

On Fri, Jan 13, 2017 at 5:44 AM, C├ędric Le Goater <clg at kaod.org> wrote:
> Hello Robert,
> On 01/10/2017 11:55 PM, Robert Lippert wrote:
>> Adds support for dual IO SPI mode.  This speeds up SPI accesses, dropping
>> time to dump an entire 64MB Macronix chip from ~12s to ~6s using:
>>       dd if=/dev/mtdblock0 bs=64MB count=1 of=/dev/null
>> The dual IO bit mode should not depend on any board-specific properties
>> as it uses the same IO lines as single bit mode.  Only issue could be
>> if a board used a one-way level tranlator or mux on the MOSI line
>> but that seems unlikely to me.
>> Tested on Zaius board with AST2500 chip, not tested on AST2400 but I
>> expect it to work since registers are identical.
>> Note dropped TODO about quad mode since ASPEED SPI controller does
>> not support quad mode.
>> Changes in v2:
>> - Cleanups suggested by Cedric.
> could you please give a quick try to this kernel :
>         https://github.com/legoater/linux/commits/openbmc-4.7
> This is an openbmc 4.7 kernel with a backport of the mainline smc
> driver, dma support, fastread support and your dual io support.
> I have tested it on a palmetto and an ast2500 evb but I don't have
> the HW you use.

Tested it after fixing a compilation error for
s/CONTROL_SPI_IO/CONTROL_IO/ and it works on Zaius board.

But it seems to be a bit slower, about half as fast as I saw before.
I think it is due to your branch missing this commit from the openbmc

423ac0dc0117f411244c38b7a351664a4c30c19a mtd: spi-nor: aspeed: rework
io routines


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