[PATCH linux 1/2] arm: aspeed: zaius: Reset PHY regardless of board revision

[Xo Wang]

Since there isn't yet an implementation of PHY hard reset in net
drivers, Zaius BMC continues to rely on the machine driver for PHY hard
reset on the EVT2 board revision.
Updates driver to assert PHY reset regardless of board revision bits.

Signed-off-by: Xo Wang <xow at google.com>
---
 arch/arm/mach-aspeed/aspeed.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 807ccc2fa28d..e4150c8a5d8d 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -136,6 +136,8 @@ static void __init do_zaius_setup(void)
 {
 	unsigned long reg;
 	unsigned long board_rev;
+	/* D3 in GPIOA/B/C/D direction and data registers */
+	unsigned long phy_reset_mask = BIT(27);
 
 	do_common_setup();
 
@@ -145,26 +147,23 @@ static void __init do_zaius_setup(void)
 
 	/* EVT1 hacks */
 	if (board_rev == 0) {
-		/* D3 in GPIOA/B/C/D direction and data registers */
-		unsigned long phy_reset_mask = BIT(27);
-
 		/* Disable GPIO I, G/AB pulldowns due to weak driving buffers */
 		reg = readl(AST_IO(AST_BASE_SCU | 0x8C));
 		writel(reg | BIT(24) | BIT(22), AST_IO(AST_BASE_SCU | 0x8C));
-
-		/* Assert MAC2 PHY hardware reset */
-		/* Set pin low */
-		reg = readl(AST_IO(AST_BASE_GPIO | 0x00));
-		writel(reg & ~phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00));
-		/* Enable pin for output */
-		reg = readl(AST_IO(AST_BASE_GPIO | 0x04));
-		writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x04));
-		udelay(3);
-		/* Set pin high */
-		reg = readl(AST_IO(AST_BASE_GPIO | 0x00));
-		writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00));
 	}
 
+	/* Assert MAC2 PHY hardware reset */
+	/* Set pin low */
+	reg = readl(AST_IO(AST_BASE_GPIO | 0x00));
+	writel(reg & ~phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00));
+	/* Enable pin for output */
+	reg = readl(AST_IO(AST_BASE_GPIO | 0x04));
+	writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x04));
+	udelay(3);
+	/* Set pin high */
+	reg = readl(AST_IO(AST_BASE_GPIO | 0x00));
+	writel(reg | phy_reset_mask, AST_IO(AST_BASE_GPIO | 0x00));
+
 	/* Setup PNOR address mapping for 64M flash
 	 *
 	 *   ADRBASE: 0x3000 (0x30000000)
-- 
2.11.0.390.gc69c2f50cf-goog