[PATCH linux dev-4.7 1/3] ARM: dts: aspeed-g5: Add SoC Display Controller node

[Andrew Jeffery]

On Mon, 2017-02-13 at 11:24 -0600, Patrick Williams wrote:
> On Mon, Feb 13, 2017 at 01:28:49PM +1030, Andrew Jeffery wrote:
> > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> > index e1994c9e38c3..5ce0a7a65e77 100644
> > --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> > @@ -1005,6 +1005,12 @@
> > > >  				reg = <0x1e6e202c 0x4>;
> > > >  			};
> >  
> > > > > > +			gfx: display at 1e6e6000 {
> > > > +				compatible = "aspeed,ast2500-gfx", "syscon";
> > > > +				reg = <0x1e6e6000 0x1000>;
> > > > +				reg-io-width = <4>;
> > > > +			};
> > +
> 


>   I believe Zaius is using a
> variant of the 2500 that does not have the graphics engine.

According to Rick, Zaius is using the AST2500 for the EVT but in the
future they will be looking at moving to a chip without the graphics
engine.

> Is this valid to add on all G5 chips?

Not on the AST2520 according to the marketing material[1]. I would
prefer to use the datasheet for the SoC as a reference though, and I
don't have an AST2520 datasheet.

The fix *should* just be a matter of a small change to the pinctrl
bindings, and we can do this when we come to support the AST2520.

Andrew

[1] https://www.aspeedtech.com/products.php?fPath=20&rId=456


> 
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 801 bytes
Desc: This is a digitally signed message part
URL: <http://lists.ozlabs.org/pipermail/openbmc/attachments/20170214/613d5037/attachment.sig>