[PATCH linux dev-4.7 08/14] pinctrl: aspeed: Reset to mainline
Andrew Jeffery
andrew at aj.id.au
Fri Feb 3 15:20:07 AEDT 2017
Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1098 +--------------------
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1476 +---------------------------
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 73 +-
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 21 +-
4 files changed, 28 insertions(+), 2640 deletions(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 921c57d445b7..a21b071ff290 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -43,18 +43,9 @@
* Not all pins have their signals defined (yet).
*/
-#define D6 0
-SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
-
-#define B5 1
-SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
-
#define A4 2
SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
-#define E6 3
-SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
-
#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
#define C5 4
@@ -89,30 +80,10 @@ MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8);
FUNC_GROUP_DECL(TIMER8, D5);
FUNC_GROUP_DECL(MDIO2, A3, D5);
-#define J21 8
-SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8));
-
-#define J20 9
-SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9));
-
-#define H18 10
-SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10));
-
-#define F18 11
-SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11));
-
-#define E19 12
-SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12));
-SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
-SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS);
-SS_PIN_DECL(E19, GPIOB4, LPCRST);
-
-FUNC_GROUP_DECL(LPCRST, E19);
-
#define H19 13
#define H19_DESC SIG_DESC_SET(SCU80, 13)
-SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC, SIG_DESC_BIT(SIORD30, 1, 0));
-SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC, SIG_DESC_SET(SIORD30, 1));
+SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC);
MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI);
FUNC_GROUP_DECL(LPCPD, H19);
@@ -121,19 +92,6 @@ FUNC_GROUP_DECL(LPCSMI, H19);
#define H20 14
SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
-#define E18 15
-SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST,
- SIG_DESC_SET(SCU80, 15),
- SIG_DESC_BIT(SCU90, 31, 0),
- SIG_DESC_SET(SCU3C, 3));
-SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1,
- SIG_DESC_SET(SCU80, 15),
- SIG_DESC_SET(SCU90, 31));
-MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1);
-
-FUNC_GROUP_DECL(EXTRST, E18);
-FUNC_GROUP_DECL(SPICS1, E18);
-
#define SD1_DESC SIG_DESC_SET(SCU90, 0)
#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
@@ -212,62 +170,6 @@ MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT);
FUNC_GROUP_DECL(GPID0, A18, D16);
-#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
-
-#define B17 26
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
-SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
-MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN);
-
-#define A17 27
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
-SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
-MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT);
-
-FUNC_GROUP_DECL(GPID2, B17, A17);
-
-#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
-
-#define C16 28
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
-SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
-MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN);
-
-#define B16 29
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
-SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
-MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT);
-
-FUNC_GROUP_DECL(GPID4, C16, B16);
-
-#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
-
-#define A16 30
-SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
-SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
-MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN);
-
-#define E15 31
-SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
-SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
-MS_PIN_DECL(E15, GPIOD7, SD2WP, GPID6OUT);
-
-FUNC_GROUP_DECL(GPID6, A16, E15);
-FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15);
-FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15);
-
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
@@ -364,15 +266,6 @@ MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI);
FUNC_GROUP_DECL(NDCD4, B19);
FUNC_GROUP_DECL(SIOPBI, B19);
-#define A20 42
-SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
-SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12));
-SIG_EXPR_DECL(SIOPWRGD, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
-MS_PIN_DECL(A20, GPIOF2, NDSR4, SIOPWRGD);
-FUNC_GROUP_DECL(NDSR4, A20);
-FUNC_GROUP_DECL(SIOPWRGD, A20);
-
#define D17 43
SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14));
@@ -382,17 +275,7 @@ MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO);
FUNC_GROUP_DECL(NRI4, D17);
FUNC_GROUP_DECL(SIOPBO, D17);
-#define B18 44
-SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28));
-
-#define A19 45
-SIG_EXPR_LIST_DECL_SINGLE(NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29));
-SIG_EXPR_DECL(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15));
-SIG_EXPR_DECL(SIOSCI, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
-MS_PIN_DECL(A19, GPIOF5, NDTS4, SIOSCI);
-FUNC_GROUP_DECL(NDTS4, A19);
-FUNC_GROUP_DECL(SIOSCI, A19);
+FUNC_GROUP_DECL(ACPI, B19, D17);
#define E16 46
SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
@@ -400,34 +283,6 @@ SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
#define C17 47
SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31));
-#define A14 48
-SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0));
-
-#define E13 49
-SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1));
-
-#define D13 50
-SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2));
-
-#define C13 51
-SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3));
-
-#define B13 52
-SIG_EXPR_LIST_DECL_SINGLE(OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1));
-SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4));
-MS_PIN_DECL(B13, GPIOG4, OSCCLK, WDTRST1);
-
-FUNC_GROUP_DECL(OSCCLK, B13);
-FUNC_GROUP_DECL(WDTRST1, B13);
-
-#define Y21 53
-SIG_EXPR_LIST_DECL_SINGLE(USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
-SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5));
-MS_PIN_DECL(Y21, GPIOG5, USBCKI, WDTRST2);
-
-FUNC_GROUP_DECL(USBCKI, Y21);
-FUNC_GROUP_DECL(WDTRST2, Y21);
-
#define AA22 54
SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6));
@@ -497,90 +352,6 @@ MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6);
FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
-#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
-#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
-#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
-
-#define C22 64
-SIG_EXPR_DECL(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
-SS_PIN_DECL(C22, GPIOI0, SYSCS);
-
-#define G18 65
-SIG_EXPR_DECL(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
-SS_PIN_DECL(G18, GPIOI1, SYSCK);
-
-#define D19 66
-SIG_EXPR_DECL(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SYSDO, SPI1DEBUG, SPI1PASSTHRU);
-SS_PIN_DECL(D19, GPIOI2, SYSDO);
-
-#define C20 67
-SIG_EXPR_DECL(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SYSDI, SPI1DEBUG, SPI1PASSTHRU);
-SS_PIN_DECL(C20, GPIOI3, SYSDI);
-
-#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
-
-#define B22 68
-SIG_EXPR_DECL(SPI1CS0, SPI1, SPI1_DESC);
-SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
- SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
- SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
-SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, VB_DESC);
-MS_PIN_DECL(B22, GPIOI4, SPI1CS0, VBCS);
-
-#define G19 69
-SIG_EXPR_DECL(SPI1CK, SPI1, SPI1_DESC);
-SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
- SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
- SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
-SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, VB_DESC);
-MS_PIN_DECL(G19, GPIOI5, SPI1CK, VBCK);
-
-#define C18 70
-SIG_EXPR_DECL(SPI1DO, SPI1, SPI1_DESC);
-SIG_EXPR_DECL(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL(SPI1DO, SIG_EXPR_PTR(SPI1DO, SPI1),
- SIG_EXPR_PTR(SPI1DO, SPI1DEBUG),
- SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU));
-SIG_EXPR_LIST_DECL_SINGLE(VBDO, VGABIOS_ROM, VB_DESC);
-MS_PIN_DECL(C18, GPIOI6, SPI1DO, VBDO);
-
-#define E20 71
-SIG_EXPR_DECL(SPI1DI, SPI1, SPI1_DESC);
-SIG_EXPR_DECL(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC);
-SIG_EXPR_DECL(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
-SIG_EXPR_LIST_DECL(SPI1DI, SIG_EXPR_PTR(SPI1DI, SPI1),
- SIG_EXPR_PTR(SPI1DI, SPI1DEBUG),
- SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU));
-SIG_EXPR_LIST_DECL_SINGLE(VBDI, VGABIOS_ROM, VB_DESC);
-MS_PIN_DECL(E20, GPIOI7, SPI1DI, VBDI);
-
-FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20);
-FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20);
-FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20);
-FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20);
-
-#define J5 72
-SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8));
-
-#define J4 73
-SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9));
-
-#define K5 74
-SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10));
-
#define J3 75
SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11));
@@ -725,102 +496,6 @@ SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC);
MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1);
FUNC_GROUP_DECL(RXD1, U5);
-#define V3 96
-#define V3_DESC SIG_DESC_SET(SCU84, 24)
-SIG_EXPR_DECL(VPIOB2, VPI18, VPI18_DESC, V3_DESC);
-SIG_EXPR_DECL(VPIOB2, VPI24, VPI24_DESC, V3_DESC);
-SIG_EXPR_DECL(VPIOB2, VPI30, VPI30_DESC, V3_DESC);
-SIG_EXPR_LIST_DECL(VPIOB2, SIG_EXPR_PTR(VPIOB2, VPI18),
- SIG_EXPR_PTR(VPIOB2, VPI24),
- SIG_EXPR_PTR(VPIOB2, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, V3_DESC);
-MS_PIN_DECL(V3, GPIOM0, VPIOB2, NCTS2);
-FUNC_GROUP_DECL(NCTS2, V3);
-
-#define W2 97
-#define W2_DESC SIG_DESC_SET(SCU84, 25)
-SIG_EXPR_DECL(VPIOB3, VPI18, VPI18_DESC, W2_DESC);
-SIG_EXPR_DECL(VPIOB3, VPI24, VPI24_DESC, W2_DESC);
-SIG_EXPR_DECL(VPIOB3, VPI30, VPI30_DESC, W2_DESC);
-SIG_EXPR_LIST_DECL(VPIOB3, SIG_EXPR_PTR(VPIOB3, VPI18),
- SIG_EXPR_PTR(VPIOB3, VPI24),
- SIG_EXPR_PTR(VPIOB3, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, W2_DESC);
-MS_PIN_DECL(W2, GPIOM1, VPIOB3, NDCD2);
-FUNC_GROUP_DECL(NDCD2, W2);
-
-#define Y1 98
-#define Y1_DESC SIG_DESC_SET(SCU84, 26)
-SIG_EXPR_DECL(VPIOB4, VPI18, VPI18_DESC, Y1_DESC);
-SIG_EXPR_DECL(VPIOB4, VPI24, VPI24_DESC, Y1_DESC);
-SIG_EXPR_DECL(VPIOB4, VPI30, VPI30_DESC, Y1_DESC);
-SIG_EXPR_LIST_DECL(VPIOB4, SIG_EXPR_PTR(VPIOB4, VPI18),
- SIG_EXPR_PTR(VPIOB4, VPI24),
- SIG_EXPR_PTR(VPIOB4, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, Y1_DESC);
-MS_PIN_DECL(Y1, GPIOM2, VPIOB4, NDSR2);
-FUNC_GROUP_DECL(NDSR2, Y1);
-
-#define V4 99
-#define V4_DESC SIG_DESC_SET(SCU84, 27)
-SIG_EXPR_DECL(VPIOB5, VPI18, VPI18_DESC, V4_DESC);
-SIG_EXPR_DECL(VPIOB5, VPI24, VPI24_DESC, V4_DESC);
-SIG_EXPR_DECL(VPIOB5, VPI30, VPI30_DESC, V4_DESC);
-SIG_EXPR_LIST_DECL(VPIOB5, SIG_EXPR_PTR(VPIOB5, VPI18),
- SIG_EXPR_PTR(VPIOB5, VPI24),
- SIG_EXPR_PTR(VPIOB5, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, V4_DESC);
-MS_PIN_DECL(V4, GPIOM3, VPIOB5, NRI2);
-FUNC_GROUP_DECL(NRI2, V4);
-
-#define W3 100
-#define W3_DESC SIG_DESC_SET(SCU84, 28)
-SIG_EXPR_DECL(VPIOB6, VPI18, VPI18_DESC, W3_DESC);
-SIG_EXPR_DECL(VPIOB6, VPI24, VPI24_DESC, W3_DESC);
-SIG_EXPR_DECL(VPIOB6, VPI30, VPI30_DESC, W3_DESC);
-SIG_EXPR_LIST_DECL(VPIOB6, SIG_EXPR_PTR(VPIOB6, VPI18),
- SIG_EXPR_PTR(VPIOB6, VPI24),
- SIG_EXPR_PTR(VPIOB6, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, W3_DESC);
-MS_PIN_DECL(W3, GPIOM4, VPIOB6, NDTR2);
-FUNC_GROUP_DECL(NDTR2, W3);
-
-#define Y2 101
-#define Y2_DESC SIG_DESC_SET(SCU84, 29)
-SIG_EXPR_DECL(VPIOB7, VPI18, VPI18_DESC, Y2_DESC);
-SIG_EXPR_DECL(VPIOB7, VPI24, VPI24_DESC, Y2_DESC);
-SIG_EXPR_DECL(VPIOB7, VPI30, VPI30_DESC, Y2_DESC);
-SIG_EXPR_LIST_DECL(VPIOB7, SIG_EXPR_PTR(VPIOB7, VPI18),
- SIG_EXPR_PTR(VPIOB7, VPI24),
- SIG_EXPR_PTR(VPIOB7, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, Y2_DESC);
-MS_PIN_DECL(Y2, GPIOM5, VPIOB7, NRTS2);
-FUNC_GROUP_DECL(NRTS2, Y2);
-
-#define AA1 102
-#define AA1_DESC SIG_DESC_SET(SCU84, 30)
-SIG_EXPR_DECL(VPIOB8, VPI18, VPI18_DESC, AA1_DESC);
-SIG_EXPR_DECL(VPIOB8, VPI24, VPI24_DESC, AA1_DESC);
-SIG_EXPR_DECL(VPIOB8, VPI30, VPI30_DESC, AA1_DESC);
-SIG_EXPR_LIST_DECL(VPIOB8, SIG_EXPR_PTR(VPIOB8, VPI18),
- SIG_EXPR_PTR(VPIOB8, VPI24),
- SIG_EXPR_PTR(VPIOB8, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, AA1_DESC);
-MS_PIN_DECL(AA1, GPIOM6, VPIOB8, TXD2);
-FUNC_GROUP_DECL(TXD2, AA1);
-
-#define V5 103
-#define V5_DESC SIG_DESC_SET(SCU84, 31)
-SIG_EXPR_DECL(VPIOB9, VPI18, VPI18_DESC, V5_DESC);
-SIG_EXPR_DECL(VPIOB9, VPI24, VPI24_DESC, V5_DESC);
-SIG_EXPR_DECL(VPIOB9, VPI30, VPI30_DESC, V5_DESC);
-SIG_EXPR_LIST_DECL(VPIOB9, SIG_EXPR_PTR(VPIOB9, VPI18),
- SIG_EXPR_PTR(VPIOB9, VPI24),
- SIG_EXPR_PTR(VPIOB9, VPI30));
-SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, V5_DESC);
-MS_PIN_DECL(V5, GPIOM7, VPIOB9, RXD2);
-FUNC_GROUP_DECL(RXD2, V5);
-
#define W4 104
#define W4_DESC SIG_DESC_SET(SCU88, 0)
SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC);
@@ -905,57 +580,10 @@ SS_PIN_DECL(V6, GPIOO0, VPIG8);
SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9));
SS_PIN_DECL(Y5, GPIOO1, VPIG9);
-#define AA4 114
-SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10));
-SS_PIN_DECL(AA4, GPIOO2, VPIR0);
-
-#define AB3 115
-SIG_EXPR_LIST_DECL_SINGLE(VPIR1, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 11));
-SS_PIN_DECL(AB3, GPIOO3, VPIR1);
-
-#define W6 116
-SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12));
-SS_PIN_DECL(W6, GPIOO4, VPIR2);
-
-#define AA5 117
-SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13));
-SS_PIN_DECL(AA5, GPIOO5, VPIR3);
-
-#define AB4 118
-SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14));
-SS_PIN_DECL(AB4, GPIOO6, VPIR4);
-
-#define V7 119
-SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15));
-SS_PIN_DECL(V7, GPIOO7, VPIR5);
-
-#define Y6 120
-SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16));
-SS_PIN_DECL(Y6, GPIOP0, VPIR6);
-
-#define AB5 121
-SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17));
-SS_PIN_DECL(AB5, GPIOP1, VPIR7);
-
-#define W7 122
-SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18));
-SS_PIN_DECL(W7, GPIOP2, VPIR8);
-
-#define AA6 123
-SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19));
-SS_PIN_DECL(AA6, GPIOP3, VPIR9);
-
-FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
- AA22, W5, Y4, AA3, AB2);
-FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
- AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7,
- AA6);
-FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1,
- V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3);
-
-#define AB6 124
-SIG_EXPR_LIST_DECL_SINGLE(GPIOP4, GPIOP4);
-MS_PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(GPIOP4));
+FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2);
+FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5);
+FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3,
+ AB2);
#define Y7 125
SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5);
@@ -991,18 +619,6 @@ SS_PIN_DECL(F5, GPIOQ3, SDA4);
FUNC_GROUP_DECL(I2C4, B1, F5);
-#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
-
-#define H4 132
-SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
-SS_PIN_DECL(H4, GPIOQ4, SCL14);
-
-#define H3 133
-SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
-SS_PIN_DECL(H3, GPIOQ5, SDA14);
-
-FUNC_GROUP_DECL(I2C14, H4, H3);
-
#define DASH9028_DESC SIG_DESC_SET(SCU90, 28)
#define H2 134
@@ -1160,6 +776,13 @@ SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8),
SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF);
MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5);
+FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
+ U19);
+FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
+ A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19);
+FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20);
+FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22);
+
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
#define A12 152
@@ -1204,50 +827,6 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13),
SIG_EXPR_LIST_PTR(RGMII1TXD3));
-#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
-
-#define D9 158
-SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2);
-MS_PIN_DECL_(D9, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2TXEN),
- SIG_EXPR_LIST_PTR(RGMII2TXCK));
-
-#define E9 159
-SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
-SIG_EXPR_LIST_DECL_SINGLE(DASHE9, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2);
-MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(DASHE9),
- SIG_EXPR_LIST_PTR(RGMII2TXCTL));
-
-#define A10 160
-SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2);
-MS_PIN_DECL_(A10, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0),
- SIG_EXPR_LIST_PTR(RGMII2TXD0));
-
-#define B10 161
-SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2);
-MS_PIN_DECL_(B10, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1),
- SIG_EXPR_LIST_PTR(RGMII2TXD1));
-
-#define C10 162
-SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
-SIG_EXPR_LIST_DECL_SINGLE(DASHC10, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2);
-MS_PIN_DECL_(C10, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(DASHC10),
- SIG_EXPR_LIST_PTR(RGMII2TXD2));
-
-#define D10 163
-SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
-SIG_EXPR_LIST_DECL_SINGLE(DASHD10, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2);
-MS_PIN_DECL_(D10, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(DASHD10),
- SIG_EXPR_LIST_PTR(RGMII2TXD3));
-
#define E11 164
SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC);
@@ -1290,419 +869,11 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
SIG_EXPR_LIST_PTR(RGMII1RXD3));
-#define C9 170
-SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLK, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2);
-MS_PIN_DECL_(C9, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLK),
- SIG_EXPR_LIST_PTR(RGMII2RXCK));
-
-#define B9 171
-SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
-SIG_EXPR_LIST_DECL_SINGLE(DASHB9, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2);
-MS_PIN_DECL_(B9, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(DASHB9),
- SIG_EXPR_LIST_PTR(RGMII2RXCTL));
-
-#define A9 172
-SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2);
-MS_PIN_DECL_(A9, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0),
- SIG_EXPR_LIST_PTR(RGMII2RXD0));
-
-#define E8 173
-SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2);
-MS_PIN_DECL_(E8, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1),
- SIG_EXPR_LIST_PTR(RGMII2RXD1));
-
-#define D8 174
-SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2);
-MS_PIN_DECL_(D8, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV),
- SIG_EXPR_LIST_PTR(RGMII2RXD2));
-
-#define C8 175
-SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
-SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2);
-MS_PIN_DECL_(C8, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
- SIG_EXPR_LIST_PTR(RGMII2RXD3));
-
FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
E10);
FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
E10);
-FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
-FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
-
-#define L5 176
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
-SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
-MS_PIN_DECL_(L5, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
-FUNC_GROUP_DECL(ADC0, L5);
-
-#define L4 177
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
-SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
-MS_PIN_DECL_(L4, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
-FUNC_GROUP_DECL(ADC1, L4);
-
-#define L3 178
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
-SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
-MS_PIN_DECL_(L3, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
-FUNC_GROUP_DECL(ADC2, L3);
-
-#define L2 179
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
-SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
-MS_PIN_DECL_(L2, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
-FUNC_GROUP_DECL(ADC3, L2);
-
-#define L1 180
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
-SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
-MS_PIN_DECL_(L1, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
-FUNC_GROUP_DECL(ADC4, L1);
-
-#define M5 181
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
-SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
-MS_PIN_DECL_(M5, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
-FUNC_GROUP_DECL(ADC5, M5);
-
-#define M4 182
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
-SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
-MS_PIN_DECL_(M4, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
-FUNC_GROUP_DECL(ADC6, M4);
-
-#define M3 183
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
-SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
-MS_PIN_DECL_(M3, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
-FUNC_GROUP_DECL(ADC7, M3);
-
-#define M2 184
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
-SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
-MS_PIN_DECL_(M2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
-FUNC_GROUP_DECL(ADC8, M2);
-
-#define M1 185
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
-SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
-MS_PIN_DECL_(M1, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
-FUNC_GROUP_DECL(ADC9, M1);
-
-#define N5 186
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
-SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
-MS_PIN_DECL_(N5, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
-FUNC_GROUP_DECL(ADC10, N5);
-
-#define N4 187
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
-SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
-MS_PIN_DECL_(N4, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
-FUNC_GROUP_DECL(ADC11, N4);
-
-#define N3 188
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
-SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
-MS_PIN_DECL_(N3, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
-FUNC_GROUP_DECL(ADC12, N3);
-
-#define N2 189
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
-SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
-MS_PIN_DECL_(N2, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
-FUNC_GROUP_DECL(ADC13, N2);
-
-#define N1 190
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
-SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
-MS_PIN_DECL_(N1, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
-FUNC_GROUP_DECL(ADC14, N1);
-
-#define P5 191
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
-SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
-MS_PIN_DECL_(P5, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
-FUNC_GROUP_DECL(ADC15, P5);
-
-#define C21 192
-SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
-SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
-SS_PIN_DECL(C21, GPIOY0, SIOS3);
-FUNC_GROUP_DECL(SIOS3, C21);
-
-#define F20 193
-SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
-SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
-SS_PIN_DECL(F20, GPIOY1, SIOS5);
-FUNC_GROUP_DECL(SIOS5, F20);
-
-#define G20 194
-SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
-SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
-SS_PIN_DECL(G20, GPIOY2, SIOPWREQ);
-FUNC_GROUP_DECL(SIOPWREQ, G20);
-
-#define K20 195
-SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
-SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
-SS_PIN_DECL(K20, GPIOY3, SIOONCTRL);
-FUNC_GROUP_DECL(SIOONCTRL, K20);
-
-FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20);
-
-#define R22 200
-#define R22_DESC SIG_DESC_SET(SCUA4, 16)
-SIG_EXPR_DECL(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA2, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB0, VPO12, R22_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB0, VPO24, R22_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB0, SIG_EXPR_PTR(VPOB0, VPO12),
- SIG_EXPR_PTR(VPOB0, VPO24), SIG_EXPR_PTR(VPOB0, VPOOFF1));
-MS_PIN_DECL(R22, GPIOZ0, ROMA2, VPOB0);
-
-#define P18 201
-#define P18_DESC SIG_DESC_SET(SCUA4, 17)
-SIG_EXPR_DECL(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA3, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB1, VPO12, P18_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB1, VPO24, P18_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB1, SIG_EXPR_PTR(VPOB1, VPO12),
- SIG_EXPR_PTR(VPOB1, VPO24), SIG_EXPR_PTR(VPOB1, VPOOFF1));
-MS_PIN_DECL(P18, GPIOZ1, ROMA3, VPOB1);
-
-#define P19 202
-#define P19_DESC SIG_DESC_SET(SCUA4, 18)
-SIG_EXPR_DECL(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA4, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB2, VPO12, P19_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB2, VPO24, P19_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO12),
- SIG_EXPR_PTR(VPOB2, VPO24), SIG_EXPR_PTR(VPOB2, VPOOFF1));
-MS_PIN_DECL(P19, GPIOZ2, ROMA4, VPOB2);
-
-#define P20 203
-#define P20_DESC SIG_DESC_SET(SCUA4, 19)
-SIG_EXPR_DECL(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA5, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB3, VPO12, P20_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB3, VPO24, P20_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO12),
- SIG_EXPR_PTR(VPOB3, VPO24), SIG_EXPR_PTR(VPOB3, VPOOFF1));
-MS_PIN_DECL(P20, GPIOZ3, ROMA5, VPOB3);
-
-#define P21 204
-#define P21_DESC SIG_DESC_SET(SCUA4, 20)
-SIG_EXPR_DECL(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA6, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB4, VPO12, P21_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB4, VPO24, P21_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO12),
- SIG_EXPR_PTR(VPOB4, VPO24), SIG_EXPR_PTR(VPOB4, VPOOFF1));
-MS_PIN_DECL(P21, GPIOZ4, ROMA6, VPOB4);
-
-#define P22 205
-#define P22_DESC SIG_DESC_SET(SCUA4, 21)
-SIG_EXPR_DECL(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA7, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB5, VPO12, P22_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB5, VPO24, P22_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO12),
- SIG_EXPR_PTR(VPOB5, VPO24), SIG_EXPR_PTR(VPOB5, VPOOFF1));
-MS_PIN_DECL(P22, GPIOZ5, ROMA7, VPOB5);
-
-#define M19 206
-#define M19_DESC SIG_DESC_SET(SCUA4, 22)
-SIG_EXPR_DECL(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA8, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB6, VPO12, M19_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB6, VPO24, M19_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO12),
- SIG_EXPR_PTR(VPOB6, VPO24), SIG_EXPR_PTR(VPOB6, VPOOFF1));
-MS_PIN_DECL(M19, GPIOZ6, ROMA8, VPOB6);
-
-#define M20 207
-#define M20_DESC SIG_DESC_SET(SCUA4, 23)
-SIG_EXPR_DECL(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA9, ROM8, ROM16);
-SIG_EXPR_DECL(VPOB7, VPO12, M20_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOB7, VPO24, M20_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO12),
- SIG_EXPR_PTR(VPOB7, VPO24), SIG_EXPR_PTR(VPOB7, VPOOFF1));
-MS_PIN_DECL(M20, GPIOZ7, ROMA9, VPOB7);
-
-#define M21 208
-#define M21_DESC SIG_DESC_SET(SCUA4, 24)
-SIG_EXPR_DECL(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA10, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG0, VPO12, M21_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOG0, VPO24, M21_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOG0, SIG_EXPR_PTR(VPOG0, VPO12),
- SIG_EXPR_PTR(VPOG0, VPO24), SIG_EXPR_PTR(VPOG0, VPOOFF1));
-MS_PIN_DECL(M21, GPIOAA0, ROMA10, VPOG0);
-
-#define M22 209
-#define M22_DESC SIG_DESC_SET(SCUA4, 25)
-SIG_EXPR_DECL(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA11, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG1, VPO12, M22_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOG1, VPO24, M22_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOG1, SIG_EXPR_PTR(VPOG1, VPO12),
- SIG_EXPR_PTR(VPOG1, VPO24), SIG_EXPR_PTR(VPOG1, VPOOFF1));
-MS_PIN_DECL(M22, GPIOAA1, ROMA11, VPOG1);
-
-#define L18 210
-#define L18_DESC SIG_DESC_SET(SCUA4, 26)
-SIG_EXPR_DECL(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA12, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG2, VPO12, L18_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOG2, VPO24, L18_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO12),
- SIG_EXPR_PTR(VPOG2, VPO24), SIG_EXPR_PTR(VPOG2, VPOOFF1));
-MS_PIN_DECL(L18, GPIOAA2, ROMA12, VPOG2);
-
-#define L19 211
-#define L19_DESC SIG_DESC_SET(SCUA4, 27)
-SIG_EXPR_DECL(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC);
-SIG_EXPR_DECL(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC);
-SIG_EXPR_LIST_DECL_DUAL(ROMA13, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG3, VPO12, L19_DESC, VPO12_DESC);
-SIG_EXPR_DECL(VPOG3, VPO24, L19_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO12),
- SIG_EXPR_PTR(VPOG3, VPO24), SIG_EXPR_PTR(VPOG3, VPOOFF1));
-MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3);
-
-#define L20 212
-#define L20_DESC SIG_DESC_SET(SCUA4, 28)
-SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOG4, VPO24, VPOOFF1);
-MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4);
-
-#define L21 213
-#define L21_DESC SIG_DESC_SET(SCUA4, 29)
-SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOG5, VPO24, VPOOFF1);
-MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5);
-
-#define T18 214
-#define T18_DESC SIG_DESC_SET(SCUA4, 30)
-SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOG6, VPO24, VPOOFF1);
-MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6);
-
-#define N18 215
-#define N18_DESC SIG_DESC_SET(SCUA4, 31)
-SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16);
-SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOG7, VPO24, VPOOFF1);
-MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7);
-
-#define N19 216
-#define N19_DESC SIG_DESC_SET(SCUA8, 0)
-SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16);
-SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOR0, VPO24, VPOOFF1);
-MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0);
-
-#define M18 217
-#define M18_DESC SIG_DESC_SET(SCUA8, 1)
-SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16);
-SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOR1, VPO24, VPOOFF1);
-MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1);
-
-#define N22 218
-#define N22_DESC SIG_DESC_SET(SCUA8, 2)
-SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16);
-SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOR2, VPO24, VPOOFF1);
-MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2);
-
-#define N20 219
-#define N20_DESC SIG_DESC_SET(SCUA8, 3)
-SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_24_OFF);
-SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_24_OFF);
-SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16);
-SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC);
-SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC);
-SIG_EXPR_LIST_DECL_DUAL(VPOR3, VPO24, VPOOFF1);
-MS_PIN_DECL(N20, GPIOAB3, ROMA21, VPOR3);
-
-FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
- U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18,
- L19, L20, L21, T18, N18, N19, M18, N22, N20);
-FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
- A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19,
- P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18,
- N18, N19, M18, N22, N20);
-FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
- M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22,
- N20);
-FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
- P20, P21, P22, M19, M20, M21, M22, L18, L19);
-
/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
* pins becomes 220.
*/
@@ -1712,180 +883,84 @@ FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(A1),
- ASPEED_PINCTRL_PIN(A10),
ASPEED_PINCTRL_PIN(A11),
ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13),
- ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
- ASPEED_PINCTRL_PIN(A16),
- ASPEED_PINCTRL_PIN(A17),
ASPEED_PINCTRL_PIN(A18),
- ASPEED_PINCTRL_PIN(A19),
ASPEED_PINCTRL_PIN(A2),
- ASPEED_PINCTRL_PIN(A20),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(A7),
ASPEED_PINCTRL_PIN(A8),
- ASPEED_PINCTRL_PIN(A9),
- ASPEED_PINCTRL_PIN(AA1),
ASPEED_PINCTRL_PIN(AA2),
ASPEED_PINCTRL_PIN(AA22),
ASPEED_PINCTRL_PIN(AA3),
- ASPEED_PINCTRL_PIN(AA4),
- ASPEED_PINCTRL_PIN(AA5),
- ASPEED_PINCTRL_PIN(AA6),
ASPEED_PINCTRL_PIN(AA7),
ASPEED_PINCTRL_PIN(AB1),
ASPEED_PINCTRL_PIN(AB2),
- ASPEED_PINCTRL_PIN(AB3),
- ASPEED_PINCTRL_PIN(AB4),
- ASPEED_PINCTRL_PIN(AB5),
- ASPEED_PINCTRL_PIN(AB6),
ASPEED_PINCTRL_PIN(AB7),
ASPEED_PINCTRL_PIN(B1),
- ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
ASPEED_PINCTRL_PIN(B12),
- ASPEED_PINCTRL_PIN(B13),
ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B15),
- ASPEED_PINCTRL_PIN(B16),
- ASPEED_PINCTRL_PIN(B17),
- ASPEED_PINCTRL_PIN(B18),
ASPEED_PINCTRL_PIN(B19),
ASPEED_PINCTRL_PIN(B2),
- ASPEED_PINCTRL_PIN(B22),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
- ASPEED_PINCTRL_PIN(B5),
ASPEED_PINCTRL_PIN(B6),
ASPEED_PINCTRL_PIN(B7),
- ASPEED_PINCTRL_PIN(B9),
ASPEED_PINCTRL_PIN(C1),
- ASPEED_PINCTRL_PIN(C10),
ASPEED_PINCTRL_PIN(C11),
ASPEED_PINCTRL_PIN(C12),
- ASPEED_PINCTRL_PIN(C13),
ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
- ASPEED_PINCTRL_PIN(C16),
ASPEED_PINCTRL_PIN(C17),
- ASPEED_PINCTRL_PIN(C18),
ASPEED_PINCTRL_PIN(C2),
- ASPEED_PINCTRL_PIN(C20),
- ASPEED_PINCTRL_PIN(C21),
- ASPEED_PINCTRL_PIN(C22),
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(C6),
ASPEED_PINCTRL_PIN(C7),
- ASPEED_PINCTRL_PIN(C8),
- ASPEED_PINCTRL_PIN(C9),
ASPEED_PINCTRL_PIN(D1),
- ASPEED_PINCTRL_PIN(D10),
ASPEED_PINCTRL_PIN(D11),
ASPEED_PINCTRL_PIN(D12),
- ASPEED_PINCTRL_PIN(D13),
ASPEED_PINCTRL_PIN(D14),
ASPEED_PINCTRL_PIN(D15),
ASPEED_PINCTRL_PIN(D16),
ASPEED_PINCTRL_PIN(D17),
ASPEED_PINCTRL_PIN(D18),
- ASPEED_PINCTRL_PIN(D19),
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D3),
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
- ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
- ASPEED_PINCTRL_PIN(D8),
- ASPEED_PINCTRL_PIN(D9),
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E11),
ASPEED_PINCTRL_PIN(E12),
- ASPEED_PINCTRL_PIN(E13),
ASPEED_PINCTRL_PIN(E14),
- ASPEED_PINCTRL_PIN(E15),
ASPEED_PINCTRL_PIN(E16),
- ASPEED_PINCTRL_PIN(E18),
- ASPEED_PINCTRL_PIN(E19),
ASPEED_PINCTRL_PIN(E2),
- ASPEED_PINCTRL_PIN(E20),
ASPEED_PINCTRL_PIN(E3),
ASPEED_PINCTRL_PIN(E5),
- ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
- ASPEED_PINCTRL_PIN(E8),
- ASPEED_PINCTRL_PIN(E9),
- ASPEED_PINCTRL_PIN(F18),
- ASPEED_PINCTRL_PIN(F20),
ASPEED_PINCTRL_PIN(F3),
ASPEED_PINCTRL_PIN(F4),
ASPEED_PINCTRL_PIN(F5),
- ASPEED_PINCTRL_PIN(G18),
- ASPEED_PINCTRL_PIN(G19),
- ASPEED_PINCTRL_PIN(G20),
ASPEED_PINCTRL_PIN(G5),
ASPEED_PINCTRL_PIN(H1),
- ASPEED_PINCTRL_PIN(H18),
ASPEED_PINCTRL_PIN(H19),
ASPEED_PINCTRL_PIN(H2),
ASPEED_PINCTRL_PIN(H20),
- ASPEED_PINCTRL_PIN(H3),
- ASPEED_PINCTRL_PIN(H4),
- ASPEED_PINCTRL_PIN(J20),
- ASPEED_PINCTRL_PIN(J21),
ASPEED_PINCTRL_PIN(J3),
- ASPEED_PINCTRL_PIN(J4),
- ASPEED_PINCTRL_PIN(J5),
ASPEED_PINCTRL_PIN(K18),
- ASPEED_PINCTRL_PIN(K20),
- ASPEED_PINCTRL_PIN(K5),
- ASPEED_PINCTRL_PIN(L1),
- ASPEED_PINCTRL_PIN(L18),
- ASPEED_PINCTRL_PIN(L19),
- ASPEED_PINCTRL_PIN(L2),
- ASPEED_PINCTRL_PIN(L20),
- ASPEED_PINCTRL_PIN(L21),
ASPEED_PINCTRL_PIN(L22),
- ASPEED_PINCTRL_PIN(L3),
- ASPEED_PINCTRL_PIN(L4),
- ASPEED_PINCTRL_PIN(L5),
- ASPEED_PINCTRL_PIN(M1),
- ASPEED_PINCTRL_PIN(M18),
- ASPEED_PINCTRL_PIN(M19),
- ASPEED_PINCTRL_PIN(M2),
- ASPEED_PINCTRL_PIN(M20),
- ASPEED_PINCTRL_PIN(M21),
- ASPEED_PINCTRL_PIN(M22),
- ASPEED_PINCTRL_PIN(M3),
- ASPEED_PINCTRL_PIN(M4),
- ASPEED_PINCTRL_PIN(M5),
- ASPEED_PINCTRL_PIN(N1),
- ASPEED_PINCTRL_PIN(N18),
- ASPEED_PINCTRL_PIN(N19),
- ASPEED_PINCTRL_PIN(N2),
- ASPEED_PINCTRL_PIN(N20),
ASPEED_PINCTRL_PIN(N21),
- ASPEED_PINCTRL_PIN(N22),
- ASPEED_PINCTRL_PIN(N3),
- ASPEED_PINCTRL_PIN(N4),
- ASPEED_PINCTRL_PIN(N5),
- ASPEED_PINCTRL_PIN(P18),
- ASPEED_PINCTRL_PIN(P19),
- ASPEED_PINCTRL_PIN(P20),
- ASPEED_PINCTRL_PIN(P21),
- ASPEED_PINCTRL_PIN(P22),
- ASPEED_PINCTRL_PIN(P5),
ASPEED_PINCTRL_PIN(R18),
- ASPEED_PINCTRL_PIN(R22),
ASPEED_PINCTRL_PIN(T1),
- ASPEED_PINCTRL_PIN(T18),
ASPEED_PINCTRL_PIN(T19),
ASPEED_PINCTRL_PIN(T2),
ASPEED_PINCTRL_PIN(T4),
@@ -1904,61 +979,28 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(V20),
ASPEED_PINCTRL_PIN(V21),
ASPEED_PINCTRL_PIN(V22),
- ASPEED_PINCTRL_PIN(V3),
- ASPEED_PINCTRL_PIN(V4),
- ASPEED_PINCTRL_PIN(V5),
ASPEED_PINCTRL_PIN(V6),
- ASPEED_PINCTRL_PIN(V7),
ASPEED_PINCTRL_PIN(W1),
- ASPEED_PINCTRL_PIN(W2),
ASPEED_PINCTRL_PIN(W21),
ASPEED_PINCTRL_PIN(W22),
- ASPEED_PINCTRL_PIN(W3),
ASPEED_PINCTRL_PIN(W4),
ASPEED_PINCTRL_PIN(W5),
- ASPEED_PINCTRL_PIN(W6),
- ASPEED_PINCTRL_PIN(W7),
- ASPEED_PINCTRL_PIN(Y1),
- ASPEED_PINCTRL_PIN(Y2),
- ASPEED_PINCTRL_PIN(Y21),
ASPEED_PINCTRL_PIN(Y22),
ASPEED_PINCTRL_PIN(Y3),
ASPEED_PINCTRL_PIN(Y4),
ASPEED_PINCTRL_PIN(Y5),
- ASPEED_PINCTRL_PIN(Y6),
ASPEED_PINCTRL_PIN(Y7),
};
static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(ACPI),
- ASPEED_PINCTRL_GROUP(ADC0),
- ASPEED_PINCTRL_GROUP(ADC1),
- ASPEED_PINCTRL_GROUP(ADC10),
- ASPEED_PINCTRL_GROUP(ADC11),
- ASPEED_PINCTRL_GROUP(ADC12),
- ASPEED_PINCTRL_GROUP(ADC13),
- ASPEED_PINCTRL_GROUP(ADC14),
- ASPEED_PINCTRL_GROUP(ADC15),
- ASPEED_PINCTRL_GROUP(ADC2),
- ASPEED_PINCTRL_GROUP(ADC3),
- ASPEED_PINCTRL_GROUP(ADC4),
- ASPEED_PINCTRL_GROUP(ADC5),
- ASPEED_PINCTRL_GROUP(ADC6),
- ASPEED_PINCTRL_GROUP(ADC7),
- ASPEED_PINCTRL_GROUP(ADC8),
- ASPEED_PINCTRL_GROUP(ADC9),
ASPEED_PINCTRL_GROUP(BMCINT),
ASPEED_PINCTRL_GROUP(DDCCLK),
ASPEED_PINCTRL_GROUP(DDCDAT),
- ASPEED_PINCTRL_GROUP(EXTRST),
ASPEED_PINCTRL_GROUP(FLACK),
ASPEED_PINCTRL_GROUP(FLBUSY),
ASPEED_PINCTRL_GROUP(FLWP),
- ASPEED_PINCTRL_GROUP(GPID),
ASPEED_PINCTRL_GROUP(GPID0),
- ASPEED_PINCTRL_GROUP(GPID2),
- ASPEED_PINCTRL_GROUP(GPID4),
- ASPEED_PINCTRL_GROUP(GPID6),
ASPEED_PINCTRL_GROUP(GPIE0),
ASPEED_PINCTRL_GROUP(GPIE2),
ASPEED_PINCTRL_GROUP(GPIE4),
@@ -1967,7 +1009,6 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
ASPEED_PINCTRL_GROUP(I2C13),
- ASPEED_PINCTRL_GROUP(I2C14),
ASPEED_PINCTRL_GROUP(I2C3),
ASPEED_PINCTRL_GROUP(I2C4),
ASPEED_PINCTRL_GROUP(I2C5),
@@ -1977,37 +1018,25 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(I2C9),
ASPEED_PINCTRL_GROUP(LPCPD),
ASPEED_PINCTRL_GROUP(LPCPME),
- ASPEED_PINCTRL_GROUP(LPCRST),
+ ASPEED_PINCTRL_GROUP(LPCPME),
ASPEED_PINCTRL_GROUP(LPCSMI),
- ASPEED_PINCTRL_GROUP(MAC1LINK),
- ASPEED_PINCTRL_GROUP(MAC2LINK),
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
ASPEED_PINCTRL_GROUP(NCTS1),
- ASPEED_PINCTRL_GROUP(NCTS2),
ASPEED_PINCTRL_GROUP(NCTS3),
ASPEED_PINCTRL_GROUP(NCTS4),
ASPEED_PINCTRL_GROUP(NDCD1),
- ASPEED_PINCTRL_GROUP(NDCD2),
ASPEED_PINCTRL_GROUP(NDCD3),
ASPEED_PINCTRL_GROUP(NDCD4),
ASPEED_PINCTRL_GROUP(NDSR1),
- ASPEED_PINCTRL_GROUP(NDSR2),
ASPEED_PINCTRL_GROUP(NDSR3),
- ASPEED_PINCTRL_GROUP(NDSR4),
ASPEED_PINCTRL_GROUP(NDTR1),
- ASPEED_PINCTRL_GROUP(NDTR2),
ASPEED_PINCTRL_GROUP(NDTR3),
- ASPEED_PINCTRL_GROUP(NDTR4),
- ASPEED_PINCTRL_GROUP(NDTS4),
ASPEED_PINCTRL_GROUP(NRI1),
- ASPEED_PINCTRL_GROUP(NRI2),
ASPEED_PINCTRL_GROUP(NRI3),
ASPEED_PINCTRL_GROUP(NRI4),
ASPEED_PINCTRL_GROUP(NRTS1),
- ASPEED_PINCTRL_GROUP(NRTS2),
ASPEED_PINCTRL_GROUP(NRTS3),
- ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM2),
@@ -2017,9 +1046,7 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(PWM6),
ASPEED_PINCTRL_GROUP(PWM7),
ASPEED_PINCTRL_GROUP(RGMII1),
- ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RMII1),
- ASPEED_PINCTRL_GROUP(RMII2),
ASPEED_PINCTRL_GROUP(ROM16),
ASPEED_PINCTRL_GROUP(ROM8),
ASPEED_PINCTRL_GROUP(ROMCS1),
@@ -2027,48 +1054,21 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(ROMCS3),
ASPEED_PINCTRL_GROUP(ROMCS4),
ASPEED_PINCTRL_GROUP(RXD1),
- ASPEED_PINCTRL_GROUP(RXD2),
ASPEED_PINCTRL_GROUP(RXD3),
ASPEED_PINCTRL_GROUP(RXD4),
- ASPEED_PINCTRL_GROUP(SALT1),
- ASPEED_PINCTRL_GROUP(SALT2),
- ASPEED_PINCTRL_GROUP(SALT3),
- ASPEED_PINCTRL_GROUP(SALT4),
ASPEED_PINCTRL_GROUP(SD1),
- ASPEED_PINCTRL_GROUP(SD2),
- ASPEED_PINCTRL_GROUP(SGPMCK),
ASPEED_PINCTRL_GROUP(SGPMI),
- ASPEED_PINCTRL_GROUP(SGPMLD),
- ASPEED_PINCTRL_GROUP(SGPMO),
- ASPEED_PINCTRL_GROUP(SGPSCK),
- ASPEED_PINCTRL_GROUP(SGPSI0),
- ASPEED_PINCTRL_GROUP(SGPSI1),
- ASPEED_PINCTRL_GROUP(SGPSLD),
- ASPEED_PINCTRL_GROUP(SIOONCTRL),
ASPEED_PINCTRL_GROUP(SIOPBI),
ASPEED_PINCTRL_GROUP(SIOPBO),
- ASPEED_PINCTRL_GROUP(SIOPWREQ),
- ASPEED_PINCTRL_GROUP(SIOPWRGD),
- ASPEED_PINCTRL_GROUP(SIOS3),
- ASPEED_PINCTRL_GROUP(SIOS5),
- ASPEED_PINCTRL_GROUP(SIOSCI),
- ASPEED_PINCTRL_GROUP(SPI1),
- ASPEED_PINCTRL_GROUP(SPI1DEBUG),
- ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
- ASPEED_PINCTRL_GROUP(SPICS1),
ASPEED_PINCTRL_GROUP(TIMER3),
- ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8),
ASPEED_PINCTRL_GROUP(TXD1),
- ASPEED_PINCTRL_GROUP(TXD2),
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
- ASPEED_PINCTRL_GROUP(USBCKI),
- ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
ASPEED_PINCTRL_GROUP(VGAHS),
ASPEED_PINCTRL_GROUP(VGAVS),
ASPEED_PINCTRL_GROUP(VPI18),
@@ -2076,40 +1076,17 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(VPI30),
ASPEED_PINCTRL_GROUP(VPO12),
ASPEED_PINCTRL_GROUP(VPO24),
- ASPEED_PINCTRL_GROUP(WDTRST1),
- ASPEED_PINCTRL_GROUP(WDTRST2),
};
static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(ACPI),
- ASPEED_PINCTRL_FUNC(ADC0),
- ASPEED_PINCTRL_FUNC(ADC1),
- ASPEED_PINCTRL_FUNC(ADC10),
- ASPEED_PINCTRL_FUNC(ADC11),
- ASPEED_PINCTRL_FUNC(ADC12),
- ASPEED_PINCTRL_FUNC(ADC13),
- ASPEED_PINCTRL_FUNC(ADC14),
- ASPEED_PINCTRL_FUNC(ADC15),
- ASPEED_PINCTRL_FUNC(ADC2),
- ASPEED_PINCTRL_FUNC(ADC3),
- ASPEED_PINCTRL_FUNC(ADC4),
- ASPEED_PINCTRL_FUNC(ADC5),
- ASPEED_PINCTRL_FUNC(ADC6),
- ASPEED_PINCTRL_FUNC(ADC7),
- ASPEED_PINCTRL_FUNC(ADC8),
- ASPEED_PINCTRL_FUNC(ADC9),
ASPEED_PINCTRL_FUNC(BMCINT),
ASPEED_PINCTRL_FUNC(DDCCLK),
ASPEED_PINCTRL_FUNC(DDCDAT),
- ASPEED_PINCTRL_FUNC(EXTRST),
ASPEED_PINCTRL_FUNC(FLACK),
ASPEED_PINCTRL_FUNC(FLBUSY),
ASPEED_PINCTRL_FUNC(FLWP),
- ASPEED_PINCTRL_FUNC(GPID),
ASPEED_PINCTRL_FUNC(GPID0),
- ASPEED_PINCTRL_FUNC(GPID2),
- ASPEED_PINCTRL_FUNC(GPID4),
- ASPEED_PINCTRL_FUNC(GPID6),
ASPEED_PINCTRL_FUNC(GPIE0),
ASPEED_PINCTRL_FUNC(GPIE2),
ASPEED_PINCTRL_FUNC(GPIE4),
@@ -2118,7 +1095,6 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
ASPEED_PINCTRL_FUNC(I2C13),
- ASPEED_PINCTRL_FUNC(I2C14),
ASPEED_PINCTRL_FUNC(I2C3),
ASPEED_PINCTRL_FUNC(I2C4),
ASPEED_PINCTRL_FUNC(I2C5),
@@ -2128,37 +1104,24 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(I2C9),
ASPEED_PINCTRL_FUNC(LPCPD),
ASPEED_PINCTRL_FUNC(LPCPME),
- ASPEED_PINCTRL_FUNC(LPCRST),
ASPEED_PINCTRL_FUNC(LPCSMI),
- ASPEED_PINCTRL_FUNC(MAC1LINK),
- ASPEED_PINCTRL_FUNC(MAC2LINK),
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
ASPEED_PINCTRL_FUNC(NCTS1),
- ASPEED_PINCTRL_FUNC(NCTS2),
ASPEED_PINCTRL_FUNC(NCTS3),
ASPEED_PINCTRL_FUNC(NCTS4),
ASPEED_PINCTRL_FUNC(NDCD1),
- ASPEED_PINCTRL_FUNC(NDCD2),
ASPEED_PINCTRL_FUNC(NDCD3),
ASPEED_PINCTRL_FUNC(NDCD4),
ASPEED_PINCTRL_FUNC(NDSR1),
- ASPEED_PINCTRL_FUNC(NDSR2),
ASPEED_PINCTRL_FUNC(NDSR3),
- ASPEED_PINCTRL_FUNC(NDSR4),
ASPEED_PINCTRL_FUNC(NDTR1),
- ASPEED_PINCTRL_FUNC(NDTR2),
ASPEED_PINCTRL_FUNC(NDTR3),
- ASPEED_PINCTRL_FUNC(NDTR4),
- ASPEED_PINCTRL_FUNC(NDTS4),
ASPEED_PINCTRL_FUNC(NRI1),
- ASPEED_PINCTRL_FUNC(NRI2),
ASPEED_PINCTRL_FUNC(NRI3),
ASPEED_PINCTRL_FUNC(NRI4),
ASPEED_PINCTRL_FUNC(NRTS1),
- ASPEED_PINCTRL_FUNC(NRTS2),
ASPEED_PINCTRL_FUNC(NRTS3),
- ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM2),
@@ -2168,9 +1131,7 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(PWM6),
ASPEED_PINCTRL_FUNC(PWM7),
ASPEED_PINCTRL_FUNC(RGMII1),
- ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RMII1),
- ASPEED_PINCTRL_FUNC(RMII2),
ASPEED_PINCTRL_FUNC(ROM16),
ASPEED_PINCTRL_FUNC(ROM8),
ASPEED_PINCTRL_FUNC(ROMCS1),
@@ -2178,48 +1139,21 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(ROMCS3),
ASPEED_PINCTRL_FUNC(ROMCS4),
ASPEED_PINCTRL_FUNC(RXD1),
- ASPEED_PINCTRL_FUNC(RXD2),
ASPEED_PINCTRL_FUNC(RXD3),
ASPEED_PINCTRL_FUNC(RXD4),
- ASPEED_PINCTRL_FUNC(SALT1),
- ASPEED_PINCTRL_FUNC(SALT2),
- ASPEED_PINCTRL_FUNC(SALT3),
- ASPEED_PINCTRL_FUNC(SALT4),
ASPEED_PINCTRL_FUNC(SD1),
- ASPEED_PINCTRL_FUNC(SD2),
- ASPEED_PINCTRL_FUNC(SGPMCK),
ASPEED_PINCTRL_FUNC(SGPMI),
- ASPEED_PINCTRL_FUNC(SGPMLD),
- ASPEED_PINCTRL_FUNC(SGPMO),
- ASPEED_PINCTRL_FUNC(SGPSCK),
- ASPEED_PINCTRL_FUNC(SGPSI0),
- ASPEED_PINCTRL_FUNC(SGPSI1),
- ASPEED_PINCTRL_FUNC(SGPSLD),
- ASPEED_PINCTRL_FUNC(SIOONCTRL),
ASPEED_PINCTRL_FUNC(SIOPBI),
ASPEED_PINCTRL_FUNC(SIOPBO),
- ASPEED_PINCTRL_FUNC(SIOPWREQ),
- ASPEED_PINCTRL_FUNC(SIOPWRGD),
- ASPEED_PINCTRL_FUNC(SIOS3),
- ASPEED_PINCTRL_FUNC(SIOS5),
- ASPEED_PINCTRL_FUNC(SIOSCI),
- ASPEED_PINCTRL_FUNC(SPI1),
- ASPEED_PINCTRL_FUNC(SPI1DEBUG),
- ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
- ASPEED_PINCTRL_FUNC(SPICS1),
ASPEED_PINCTRL_FUNC(TIMER3),
- ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8),
ASPEED_PINCTRL_FUNC(TXD1),
- ASPEED_PINCTRL_FUNC(TXD2),
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
- ASPEED_PINCTRL_FUNC(USBCKI),
- ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
ASPEED_PINCTRL_FUNC(VGAHS),
ASPEED_PINCTRL_FUNC(VGAVS),
ASPEED_PINCTRL_FUNC(VPI18),
@@ -2227,8 +1161,6 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(VPI30),
ASPEED_PINCTRL_FUNC(VPO12),
ASPEED_PINCTRL_FUNC(VPO24),
- ASPEED_PINCTRL_FUNC(WDTRST1),
- ASPEED_PINCTRL_FUNC(WDTRST2),
};
static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 9a3139c13ffc..87b46390b695 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -24,27 +24,14 @@
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
-#define ASPEED_G5_NR_PINS 232
+#define ASPEED_G5_NR_PINS 228
#define COND1 { SCU90, BIT(6), 0, 0 }
#define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
-#define LHCR0 SIG_DESC_TO_REG(ASPEED_IP_LPC, 0xA0)
-#define GFX064 SIG_DESC_TO_REG(ASPEED_IP_GFX, 0x64)
-
#define B14 0
SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
-#define D14 1
-SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
-
-#define D13 2
-SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
-SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
-MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3);
-FUNC_GROUP_DECL(SPI1CS1, D13);
-FUNC_GROUP_DECL(TIMER3, D13);
-
#define E13 3
SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
@@ -84,32 +71,6 @@ FUNC_GROUP_DECL(TIMER8, B13);
FUNC_GROUP_DECL(MDIO2, C13, B13);
-#define K19 8
-GPIO_PIN_DECL(K19, GPIOB0);
-
-#define L19 9
-GPIO_PIN_DECL(L19, GPIOB1);
-
-#define L18 10
-GPIO_PIN_DECL(L18, GPIOB2);
-
-#define K18 11
-GPIO_PIN_DECL(K18, GPIOB3);
-
-#define J20 12
-SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
-
-#define H21 13
-#define H21_DESC SIG_DESC_SET(SCU80, 13)
-SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC, SIG_DESC_BIT(SIORD30, 1, 0));
-SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC, SIG_DESC_SET(SIORD30, 1));
-MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI);
-FUNC_GROUP_DECL(LPCPD, H21);
-FUNC_GROUP_DECL(LPCSMI, H21);
-
-#define H22 14
-SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
-
#define H20 15
GPIO_PIN_DECL(H20, GPIOB7);
@@ -206,44 +167,7 @@ MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
FUNC_GROUP_DECL(GPID2, F20, D20);
-#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
-
-#define D21 28
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
-SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
-MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN);
-
-#define E20 29
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
-SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
-MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT);
-
-FUNC_GROUP_DECL(GPID4, D21, E20);
-
-#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
-
-#define G18 30
-SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
-SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
-MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN);
-
-#define C21 31
-SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
-SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
-MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT);
-
-FUNC_GROUP_DECL(GPID6, G18, C21);
-FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
-
-#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
+#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21)
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
#define B20 32
@@ -252,7 +176,6 @@ SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
-FUNC_GROUP_DECL(NCTS3, B20);
#define C20 33
SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
@@ -260,227 +183,9 @@ SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
-FUNC_GROUP_DECL(NDCD3, C20);
FUNC_GROUP_DECL(GPIE0, B20, C20);
-#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
-
-#define F18 34
-SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
-SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC);
-SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE);
-MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN);
-FUNC_GROUP_DECL(NDSR3, F18);
-
-
-#define F17 35
-SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
-SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC);
-SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE);
-MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT);
-FUNC_GROUP_DECL(NRI3, F17);
-
-FUNC_GROUP_DECL(GPIE2, F18, F17);
-
-#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
-
-#define E18 36
-SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
-SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC);
-SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE);
-MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN);
-FUNC_GROUP_DECL(NDTR3, E18);
-
-#define D19 37
-SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
-SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC);
-SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE);
-MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT);
-FUNC_GROUP_DECL(NRTS3, D19);
-
-FUNC_GROUP_DECL(GPIE4, E18, D19);
-
-#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
-
-#define A20 38
-SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
-SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC);
-SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE);
-MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN);
-FUNC_GROUP_DECL(TXD3, A20);
-
-#define B19 39
-SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
-SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC);
-SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE);
-MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT);
-FUNC_GROUP_DECL(RXD3, B19);
-
-FUNC_GROUP_DECL(GPIE6, A20, B19);
-
-#define LPCHC_DESC SIG_DESC_SET(LHCR0, 0)
-#define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
-
-#define J19 40
-SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC);
-SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC);
-SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS);
-SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
-MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4);
-FUNC_GROUP_DECL(NCTS4, J19);
-
-#define J18 41
-SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC);
-SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC);
-SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS);
-SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
-MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4);
-FUNC_GROUP_DECL(NDCD4, J18);
-
-#define B22 42
-SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC);
-SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC);
-SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS);
-SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
-MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4);
-FUNC_GROUP_DECL(NDSR4, B22);
-
-#define B21 43
-SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC);
-SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC);
-SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS);
-SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
-MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4);
-FUNC_GROUP_DECL(NRI4, B21);
-
-#define A21 44
-SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC);
-SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC);
-SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS);
-SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
-MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4);
-FUNC_GROUP_DECL(NDTR4, A21);
-
-#define H19 45
-SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC);
-SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC);
-SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS);
-SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
-MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4);
-FUNC_GROUP_DECL(NRTS4, H19);
-
-#define G17 46
-SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
-MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4);
-FUNC_GROUP_DECL(TXD4, G17);
-
-#define H18 47
-SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC);
-SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC);
-SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS);
-SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
-MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4);
-FUNC_GROUP_DECL(RXD4, H18);
-
-FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
-FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
-
-#define A19 48
-SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
-SS_PIN_DECL(A19, GPIOG0, SGPS1CK);
-
-#define E19 49
-SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
-SS_PIN_DECL(E19, GPIOG1, SGPS1LD);
-
-#define C19 50
-SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
-SS_PIN_DECL(C19, GPIOG2, SGPS1I0);
-
-#define E16 51
-SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
-SS_PIN_DECL(E16, GPIOG3, SGPS1I1);
-
-FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
-
-#define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
-
-#define E17 52
-SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
-MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1);
-FUNC_GROUP_DECL(SALT1, E17);
-
-#define D16 53
-SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
-MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2);
-FUNC_GROUP_DECL(SALT2, D16);
-
-#define D15 54
-SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
-MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3);
-FUNC_GROUP_DECL(SALT3, D15);
-
-#define E14 55
-SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
-MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4);
-FUNC_GROUP_DECL(SALT4, E14);
-
-FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
-
-#define UART6_DESC SIG_DESC_SET(SCU90, 7)
-
-#define A18 56
-SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
-SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC);
-MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6);
-
-#define B18 57
-SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
-SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC);
-MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6);
-
-#define D17 58
-SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
-SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC);
-MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6);
-
-#define C17 59
-SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
-SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC);
-MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6);
-
-#define A17 60
-SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
-SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC);
-MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6);
-
-#define B17 61
-SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
-SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC);
-MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6);
-
-#define A16 62
-SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC);
-SS_PIN_DECL(A16, GPIOH6, TXD6);
-
-#define D18 63
-SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC);
-SS_PIN_DECL(D18, GPIOH7, RXD6);
-
-FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
-
#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
@@ -572,30 +277,6 @@ SS_PIN_DECL(N3, GPIOJ2, SGPMO);
SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
SS_PIN_DECL(N4, GPIOJ3, SGPMI);
-#define N5 76
-SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
-SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
-MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5);
-FUNC_GROUP_DECL(VGAHS, N5);
-
-#define R4 77
-SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
-SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
-MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4);
-FUNC_GROUP_DECL(VGAVS, R4);
-
-#define R3 78
-SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
-SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
-MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3);
-FUNC_GROUP_DECL(DDCCLK, R3);
-
-#define T3 79
-SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
-SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
-MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3);
-FUNC_GROUP_DECL(DDCDAT, T3);
-
#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
#define L3 80
@@ -644,119 +325,10 @@ SS_PIN_DECL(R1, GPIOK7, SDA8);
FUNC_GROUP_DECL(I2C8, P2, R1);
-#define T2 88
-SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
-
#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 }
#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 }
#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 }
-#define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
-
-#define T1 89
-#define T1_DESC SIG_DESC_SET(SCU84, 17)
-SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2);
-MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1);
-FUNC_GROUP_DECL(NDCD1, T1);
-
-#define U1 90
-#define U1_DESC SIG_DESC_SET(SCU84, 18)
-SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC);
-MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1);
-FUNC_GROUP_DECL(NDSR1, U1);
-
-#define U2 91
-#define U2_DESC SIG_DESC_SET(SCU84, 19)
-SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2);
-MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1);
-FUNC_GROUP_DECL(NRI1, U2);
-
-#define P4 92
-#define P4_DESC SIG_DESC_SET(SCU84, 20)
-SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2);
-MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1);
-FUNC_GROUP_DECL(NDTR1, P4);
-
-#define P3 93
-#define P3_DESC SIG_DESC_SET(SCU84, 21)
-SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2);
-MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1);
-FUNC_GROUP_DECL(NRTS1, P3);
-
-#define V1 94
-#define V1_DESC SIG_DESC_SET(SCU84, 22)
-SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2);
-MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1);
-FUNC_GROUP_DECL(TXD1, V1);
-
-#define W1 95
-#define W1_DESC SIG_DESC_SET(SCU84, 23)
-SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2);
-MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1);
-FUNC_GROUP_DECL(RXD1, W1);
-
-#define Y1 96
-#define Y1_DESC SIG_DESC_SET(SCU84, 24)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2);
-MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2);
-FUNC_GROUP_DECL(NCTS2, Y1);
-
-#define AB2 97
-#define AB2_DESC SIG_DESC_SET(SCU84, 25)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2);
-MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2);
-FUNC_GROUP_DECL(NDCD2, AB2);
-
-#define AA1 98
-#define AA1_DESC SIG_DESC_SET(SCU84, 26)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2);
-MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2);
-FUNC_GROUP_DECL(NDSR2, AA1);
-
-#define Y2 99
-#define Y2_DESC SIG_DESC_SET(SCU84, 27)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2);
-MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2);
-FUNC_GROUP_DECL(NRI2, Y2);
-
-#define AA2 100
-#define AA2_DESC SIG_DESC_SET(SCU84, 28)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2);
-MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2);
-FUNC_GROUP_DECL(NDTR2, AA2);
-
-#define P5 101
-#define P5_DESC SIG_DESC_SET(SCU84, 29)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2);
-MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2);
-FUNC_GROUP_DECL(NRTS2, P5);
-
-#define R5 102
-#define R5_DESC SIG_DESC_SET(SCU84, 30)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2);
-MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2);
-FUNC_GROUP_DECL(TXD2, R5);
-
-#define T5 103
-#define T5_DESC SIG_DESC_SET(SCU84, 31)
-SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
-SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2);
-MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2);
-FUNC_GROUP_DECL(RXD2, T5);
#define V2 104
#define V2_DESC SIG_DESC_SET(SCU88, 0)
@@ -822,88 +394,9 @@ SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
FUNC_GROUP_DECL(PWM7, T4);
-#define U5 112
-SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
- COND2);
-SS_PIN_DECL(U5, GPIOO0, VPIG8);
-
-#define U4 113
-SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
- COND2);
-SS_PIN_DECL(U4, GPIOO1, VPIG9);
-
-#define V5 114
-SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC,
- SIG_DESC_SET(SCU88, 10));
-SS_PIN_DECL(V5, GPIOO2, DASHV5);
-
-#define AB4 115
-SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
- SIG_DESC_SET(SCU88, 11));
-SS_PIN_DECL(AB4, GPIOO3, DASHAB4);
-
-#define AB3 116
-SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12),
- COND2);
-SS_PIN_DECL(AB3, GPIOO4, VPIR2);
-
-#define Y4 117
-SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13),
- COND2);
-SS_PIN_DECL(Y4, GPIOO5, VPIR3);
-
-#define AA4 118
-SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14),
- COND2);
-SS_PIN_DECL(AA4, GPIOO6, VPIR4);
-
-#define W4 119
-SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15),
- COND2);
-SS_PIN_DECL(W4, GPIOO7, VPIR5);
-
-#define V4 120
-SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16),
- COND2);
-SS_PIN_DECL(V4, GPIOP0, VPIR6);
-
-#define W5 121
-SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17),
- COND2);
-SS_PIN_DECL(W5, GPIOP1, VPIR7);
-
-#define AA5 122
-SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18),
- COND2);
-SS_PIN_DECL(AA5, GPIOP2, VPIR8);
-
-#define AB5 123
-SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19),
- COND2);
-SS_PIN_DECL(AB5, GPIOP3, VPIR9);
-
-FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
- U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
- AB5);
-
-#define Y6 124
-SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
- SIG_DESC_SET(SCU88, 20));
-SS_PIN_DECL(Y6, GPIOP4, DASHY6);
-
-#define Y5 125
-SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
- SIG_DESC_SET(SCU88, 21));
-SS_PIN_DECL(Y5, GPIOP5, DASHY5);
-
-#define W6 126
-SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
- SIG_DESC_SET(SCU88, 22));
-SS_PIN_DECL(W6, GPIOP6, DASHW6);
-
#define V6 127
SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
- SIG_DESC_SET(SCU88, 23));
+ SIG_DESC_SET(SCU88, 23));
SS_PIN_DECL(V6, GPIOP7, DASHV6);
#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
@@ -948,24 +441,6 @@ SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
#define N20 135
SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
-#define AA19 136
-SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
-
-#define T19 137
-SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
-
-#define T17 138
-SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
-
-#define Y19 139
-SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
-
-#define W19 140
-SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
-
-#define V19 141
-SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
-
#define D8 142
SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
SS_PIN_DECL(D8, GPIOR6, MDC1);
@@ -976,93 +451,6 @@ SS_PIN_DECL(E10, GPIOR7, MDIO1);
FUNC_GROUP_DECL(MDIO1, D8, E10);
-#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 }
-#define VPO_DESC { SCU94, GENMASK(1, 0), 1, 0 }
-#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 2, 0 }
-#define VPOOFF2_DESC { SCU94, GENMASK(1, 0), 3, 0 }
-
-#define CRT_DVO_EN_DESC SIG_DESC_SET(GFX064, 7)
-
-#define V20 144
-#define V20_DESC SIG_DESC_SET(SCU8C, 0)
-SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO),
- SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC);
-MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1);
-FUNC_GROUP_DECL(SPI2CS1, V20);
-
-#define U19 145
-#define U19_DESC SIG_DESC_SET(SCU8C, 1)
-SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO),
- SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC);
-MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT);
-FUNC_GROUP_DECL(BMCINT, U19);
-
-#define R18 146
-#define R18_DESC SIG_DESC_SET(SCU8C, 2)
-SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO),
- SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC);
-MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5);
-FUNC_GROUP_DECL(SALT5, R18);
-
-#define P18 147
-#define P18_DESC SIG_DESC_SET(SCU8C, 3)
-SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO),
- SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC);
-MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6);
-FUNC_GROUP_DECL(SALT6, P18);
-
-#define R19 148
-#define R19_DESC SIG_DESC_SET(SCU8C, 4)
-SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO),
- SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2));
-SS_PIN_DECL(R19, GPIOS4, VPOB6);
-
-#define W20 149
-#define W20_DESC SIG_DESC_SET(SCU8C, 5)
-SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO),
- SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2));
-SS_PIN_DECL(W20, GPIOS5, VPOB7);
-
-#define U20 150
-#define U20_DESC SIG_DESC_SET(SCU8C, 6)
-SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO),
- SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2));
-SS_PIN_DECL(U20, GPIOS6, VPOB8);
-
-#define AA20 151
-#define AA20_DESC SIG_DESC_SET(SCU8C, 7)
-SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO),
- SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2));
-SS_PIN_DECL(AA20, GPIOS7, VPOB9);
-
/* RGMII1/RMII1 */
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
@@ -1244,481 +632,6 @@ MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
-#define F4 176
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
-SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
-MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
-FUNC_GROUP_DECL(ADC0, F4);
-
-#define F5 177
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
-SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
-MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
-FUNC_GROUP_DECL(ADC1, F5);
-
-#define E2 178
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
-SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
-MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
-FUNC_GROUP_DECL(ADC2, E2);
-
-#define E1 179
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
-SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
-MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
-FUNC_GROUP_DECL(ADC3, E1);
-
-#define F3 180
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
-SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
-MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
-FUNC_GROUP_DECL(ADC4, F3);
-
-#define E3 181
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
-SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
-MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
-FUNC_GROUP_DECL(ADC5, E3);
-
-#define G5 182
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
-SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
-MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
-FUNC_GROUP_DECL(ADC6, G5);
-
-#define G4 183
-SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
-SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
-MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
-FUNC_GROUP_DECL(ADC7, G4);
-
-#define F2 184
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
-SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
-MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
-FUNC_GROUP_DECL(ADC8, F2);
-
-#define G3 185
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
-SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
-MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
-FUNC_GROUP_DECL(ADC9, G3);
-
-#define G2 186
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
-SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
-MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
-FUNC_GROUP_DECL(ADC10, G2);
-
-#define F1 187
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
-SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
-MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
-FUNC_GROUP_DECL(ADC11, F1);
-
-#define H5 188
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
-SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
-MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
-FUNC_GROUP_DECL(ADC12, H5);
-
-#define G1 189
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
-SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
-MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
-FUNC_GROUP_DECL(ADC13, G1);
-
-#define H3 190
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
-SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
-MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
-FUNC_GROUP_DECL(ADC14, H3);
-
-#define H4 191
-SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
-SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
-MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
-FUNC_GROUP_DECL(ADC15, H4);
-
-#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
-
-#define R22 192
-SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
-SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
-MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22);
-FUNC_GROUP_DECL(SIOS3, R22);
-
-#define R21 193
-SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
-SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
-MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21);
-FUNC_GROUP_DECL(SIOS5, R21);
-
-#define P22 194
-SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
-SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
-MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22);
-FUNC_GROUP_DECL(SIOPWREQ, P22);
-
-#define P21 195
-SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
-SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
-MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21);
-FUNC_GROUP_DECL(SIOONCTRL, P21);
-
-#define M18 196
-SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
-
-#define M19 197
-SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
-
-#define M20 198
-SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
-
-#define P20 199
-SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
-
-#define PNOR_DESC SIG_DESC_SET(SCU90, 31)
-
-#define Y20 200
-#define Y20_DESC SIG_DESC_SET(SCUA4, 16)
-SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO),
- SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2));
-SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC);
-SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0);
-MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI),
- SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0));
-FUNC_GROUP_DECL(SIOPBI, Y20);
-
-#define AB20 201
-#define AB20_DESC SIG_DESC_SET(SCUA4, 17)
-SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO),
- SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2));
-SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC);
-SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1);
-MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD),
- SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1));
-FUNC_GROUP_DECL(SIOPWRGD, AB20);
-
-#define AB21 202
-#define AB21_DESC SIG_DESC_SET(SCUA4, 18)
-SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO),
- SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2));
-SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC);
-SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2);
-MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO),
- SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2));
-FUNC_GROUP_DECL(SIOPBO, AB21);
-
-#define AA21 203
-#define AA21_DESC SIG_DESC_SET(SCUA4, 19)
-SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO),
- SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2));
-SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC);
-SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC);
-SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
-SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3);
-MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI),
- SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3));
-FUNC_GROUP_DECL(SIOSCI, AA21);
-
-FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
-
-/* CRT DVO disabled, configured for single-edge mode */
-#define CRT_DVO_DS_DESC { GFX064, GENMASK(7, 6), 0, 0 }
-
-/* CRT DVO disabled, configured for dual-edge mode */
-#define CRT_DVO_DD_DESC { GFX064, GENMASK(7, 6), 1, 1 }
-
-/* CRT DVO enabled, configured for single-edge mode */
-#define CRT_DVO_ES_DESC { GFX064, GENMASK(7, 6), 2, 2 }
-
-/* CRT DVO enabled, configured for dual-edge mode */
-#define CRT_DVO_ED_DESC { GFX064, GENMASK(7, 6), 3, 3 }
-
-#define U21 204
-#define U21_DESC SIG_DESC_SET(SCUA4, 20)
-SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO),
- SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC);
-MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4);
-
-#define W22 205
-#define W22_DESC SIG_DESC_SET(SCUA4, 21)
-SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO),
- SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC);
-MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5);
-
-#define V22 206
-#define V22_DESC SIG_DESC_SET(SCUA4, 22)
-SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO),
- SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC);
-MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6);
-
-#define W21 207
-#define W21_DESC SIG_DESC_SET(SCUA4, 23)
-SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO),
- SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC);
-MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7);
-
-#define Y21 208
-#define Y21_DESC SIG_DESC_SET(SCUA4, 24)
-SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO),
- SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0);
-MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7),
- SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0));
-FUNC_GROUP_DECL(SALT7, Y21);
-
-#define V21 209
-#define V21_DESC SIG_DESC_SET(SCUA4, 25)
-SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO),
- SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1);
-MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8),
- SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1));
-FUNC_GROUP_DECL(SALT8, V21);
-
-#define Y22 210
-#define Y22_DESC SIG_DESC_SET(SCUA4, 26)
-SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO),
- SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2);
-MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9),
- SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2));
-FUNC_GROUP_DECL(SALT9, Y22);
-
-#define AA22 211
-#define AA22_DESC SIG_DESC_SET(SCUA4, 27)
-SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO),
- SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3);
-MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10),
- SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3));
-FUNC_GROUP_DECL(SALT10, AA22);
-
-#define U22 212
-#define U22_DESC SIG_DESC_SET(SCUA4, 28)
-SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO),
- SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4);
-MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11),
- SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4));
-FUNC_GROUP_DECL(SALT11, U22);
-
-#define T20 213
-#define T20_DESC SIG_DESC_SET(SCUA4, 29)
-SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO),
- SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5);
-MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12),
- SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5));
-FUNC_GROUP_DECL(SALT12, T20);
-
-#define N18 214
-#define N18_DESC SIG_DESC_SET(SCUA4, 30)
-SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO),
- SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6);
-MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13),
- SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6));
-FUNC_GROUP_DECL(SALT13, N18);
-
-#define P19 215
-#define P19_DESC SIG_DESC_SET(SCUA4, 31)
-SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
-SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO),
- SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7);
-MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14),
- SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7));
-FUNC_GROUP_DECL(SALT14, P19);
-
-#define N19 216
-#define N19_DESC SIG_DESC_SET(SCUA8, 0)
-SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO),
- SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC);
-MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE);
-
-#define T21 217
-#define T21_DESC SIG_DESC_SET(SCUA8, 1)
-SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO),
- SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC);
-MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE);
-
-FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
- AA22, U22, T20, N18, P19, N19, T21);
-
-#define T22 218
-#define T22_DESC SIG_DESC_SET(SCUA8, 2)
-SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO),
- SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC);
-MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1);
-FUNC_GROUP_DECL(WDTRST1, T22);
-
-#define R20 219
-#define R20_DESC SIG_DESC_SET(SCUA8, 3)
-SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
-SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO),
- SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2));
-SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC);
-MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2);
-FUNC_GROUP_DECL(WDTRST2, R20);
-
-FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
- AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
- N18, P19, N19, T21, T22, R20);
-
-#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
-
-#define G21 224
-SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
-MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0);
-FUNC_GROUP_DECL(LAD0, G21);
-
-#define G20 225
-SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
-MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1);
-FUNC_GROUP_DECL(LAD1, G20);
-
-#define D22 226
-SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
-MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2);
-FUNC_GROUP_DECL(LAD2, D22);
-
-#define E22 227
-SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
-MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3);
-FUNC_GROUP_DECL(LAD3, E22);
-
-#define C22 228
-SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
-MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK);
-FUNC_GROUP_DECL(LCLK, C22);
-
-#define F21 229
-SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
-MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME);
-FUNC_GROUP_DECL(LFRAME, F21);
-
-#define F22 230
-SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
-MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ);
-FUNC_GROUP_DECL(LSIRQ, F22);
-
-#define G22 231
-SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
-MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST);
-FUNC_GROUP_DECL(LPCRST, G22);
-
-FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
-
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
@@ -1728,32 +641,12 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A13),
ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
- ASPEED_PINCTRL_PIN(A16),
- ASPEED_PINCTRL_PIN(A17),
- ASPEED_PINCTRL_PIN(A18),
- ASPEED_PINCTRL_PIN(A19),
ASPEED_PINCTRL_PIN(A2),
- ASPEED_PINCTRL_PIN(A20),
- ASPEED_PINCTRL_PIN(A21),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A9),
- ASPEED_PINCTRL_PIN(AA1),
- ASPEED_PINCTRL_PIN(AA19),
- ASPEED_PINCTRL_PIN(AA2),
- ASPEED_PINCTRL_PIN(AA20),
- ASPEED_PINCTRL_PIN(AA21),
- ASPEED_PINCTRL_PIN(AA22),
ASPEED_PINCTRL_PIN(AA3),
- ASPEED_PINCTRL_PIN(AA4),
- ASPEED_PINCTRL_PIN(AA5),
- ASPEED_PINCTRL_PIN(AB2),
- ASPEED_PINCTRL_PIN(AB20),
- ASPEED_PINCTRL_PIN(AB21),
- ASPEED_PINCTRL_PIN(AB3),
- ASPEED_PINCTRL_PIN(AB4),
- ASPEED_PINCTRL_PIN(AB5),
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
@@ -1762,13 +655,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B15),
ASPEED_PINCTRL_PIN(B16),
- ASPEED_PINCTRL_PIN(B17),
- ASPEED_PINCTRL_PIN(B18),
- ASPEED_PINCTRL_PIN(B19),
ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B20),
- ASPEED_PINCTRL_PIN(B21),
- ASPEED_PINCTRL_PIN(B22),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B5),
@@ -1780,210 +668,62 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
ASPEED_PINCTRL_PIN(C16),
- ASPEED_PINCTRL_PIN(C17),
ASPEED_PINCTRL_PIN(C18),
- ASPEED_PINCTRL_PIN(C19),
ASPEED_PINCTRL_PIN(C2),
ASPEED_PINCTRL_PIN(C20),
- ASPEED_PINCTRL_PIN(C21),
- ASPEED_PINCTRL_PIN(C22),
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(D1),
ASPEED_PINCTRL_PIN(D10),
- ASPEED_PINCTRL_PIN(D13),
- ASPEED_PINCTRL_PIN(D14),
- ASPEED_PINCTRL_PIN(D15),
- ASPEED_PINCTRL_PIN(D16),
- ASPEED_PINCTRL_PIN(D17),
- ASPEED_PINCTRL_PIN(D18),
- ASPEED_PINCTRL_PIN(D19),
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D20),
- ASPEED_PINCTRL_PIN(D21),
- ASPEED_PINCTRL_PIN(D22),
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
ASPEED_PINCTRL_PIN(D8),
ASPEED_PINCTRL_PIN(D9),
- ASPEED_PINCTRL_PIN(E1),
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E12),
ASPEED_PINCTRL_PIN(E13),
- ASPEED_PINCTRL_PIN(E14),
ASPEED_PINCTRL_PIN(E15),
- ASPEED_PINCTRL_PIN(E16),
- ASPEED_PINCTRL_PIN(E17),
- ASPEED_PINCTRL_PIN(E18),
- ASPEED_PINCTRL_PIN(E19),
- ASPEED_PINCTRL_PIN(E2),
- ASPEED_PINCTRL_PIN(E20),
ASPEED_PINCTRL_PIN(E21),
- ASPEED_PINCTRL_PIN(E22),
- ASPEED_PINCTRL_PIN(E3),
ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
ASPEED_PINCTRL_PIN(E9),
- ASPEED_PINCTRL_PIN(F1),
- ASPEED_PINCTRL_PIN(F17),
- ASPEED_PINCTRL_PIN(F18),
ASPEED_PINCTRL_PIN(F19),
- ASPEED_PINCTRL_PIN(F2),
ASPEED_PINCTRL_PIN(F20),
- ASPEED_PINCTRL_PIN(F21),
- ASPEED_PINCTRL_PIN(F22),
- ASPEED_PINCTRL_PIN(F3),
- ASPEED_PINCTRL_PIN(F4),
- ASPEED_PINCTRL_PIN(F5),
ASPEED_PINCTRL_PIN(F9),
- ASPEED_PINCTRL_PIN(G1),
- ASPEED_PINCTRL_PIN(G17),
- ASPEED_PINCTRL_PIN(G18),
- ASPEED_PINCTRL_PIN(G2),
- ASPEED_PINCTRL_PIN(G20),
- ASPEED_PINCTRL_PIN(G21),
- ASPEED_PINCTRL_PIN(G22),
- ASPEED_PINCTRL_PIN(G3),
- ASPEED_PINCTRL_PIN(G4),
- ASPEED_PINCTRL_PIN(G5),
- ASPEED_PINCTRL_PIN(H18),
- ASPEED_PINCTRL_PIN(H19),
ASPEED_PINCTRL_PIN(H20),
- ASPEED_PINCTRL_PIN(H21),
- ASPEED_PINCTRL_PIN(H22),
- ASPEED_PINCTRL_PIN(H3),
- ASPEED_PINCTRL_PIN(H4),
- ASPEED_PINCTRL_PIN(H5),
- ASPEED_PINCTRL_PIN(J18),
- ASPEED_PINCTRL_PIN(J19),
- ASPEED_PINCTRL_PIN(J20),
- ASPEED_PINCTRL_PIN(K18),
- ASPEED_PINCTRL_PIN(K19),
ASPEED_PINCTRL_PIN(L1),
- ASPEED_PINCTRL_PIN(L18),
- ASPEED_PINCTRL_PIN(L19),
ASPEED_PINCTRL_PIN(L2),
ASPEED_PINCTRL_PIN(L3),
ASPEED_PINCTRL_PIN(L4),
- ASPEED_PINCTRL_PIN(M18),
- ASPEED_PINCTRL_PIN(M19),
- ASPEED_PINCTRL_PIN(M20),
ASPEED_PINCTRL_PIN(N1),
- ASPEED_PINCTRL_PIN(N18),
- ASPEED_PINCTRL_PIN(N19),
ASPEED_PINCTRL_PIN(N2),
ASPEED_PINCTRL_PIN(N20),
ASPEED_PINCTRL_PIN(N21),
ASPEED_PINCTRL_PIN(N22),
ASPEED_PINCTRL_PIN(N3),
ASPEED_PINCTRL_PIN(N4),
- ASPEED_PINCTRL_PIN(N5),
ASPEED_PINCTRL_PIN(P1),
- ASPEED_PINCTRL_PIN(P18),
- ASPEED_PINCTRL_PIN(P19),
ASPEED_PINCTRL_PIN(P2),
- ASPEED_PINCTRL_PIN(P20),
- ASPEED_PINCTRL_PIN(P21),
- ASPEED_PINCTRL_PIN(P22),
- ASPEED_PINCTRL_PIN(P3),
- ASPEED_PINCTRL_PIN(P4),
- ASPEED_PINCTRL_PIN(P5),
ASPEED_PINCTRL_PIN(R1),
- ASPEED_PINCTRL_PIN(R18),
- ASPEED_PINCTRL_PIN(R19),
- ASPEED_PINCTRL_PIN(R2),
- ASPEED_PINCTRL_PIN(R20),
- ASPEED_PINCTRL_PIN(R21),
- ASPEED_PINCTRL_PIN(R22),
- ASPEED_PINCTRL_PIN(R3),
- ASPEED_PINCTRL_PIN(R4),
- ASPEED_PINCTRL_PIN(R5),
- ASPEED_PINCTRL_PIN(T1),
- ASPEED_PINCTRL_PIN(T17),
- ASPEED_PINCTRL_PIN(T19),
- ASPEED_PINCTRL_PIN(T2),
- ASPEED_PINCTRL_PIN(T20),
- ASPEED_PINCTRL_PIN(T21),
- ASPEED_PINCTRL_PIN(T22),
- ASPEED_PINCTRL_PIN(T3),
ASPEED_PINCTRL_PIN(T4),
- ASPEED_PINCTRL_PIN(T5),
- ASPEED_PINCTRL_PIN(U1),
- ASPEED_PINCTRL_PIN(U19),
- ASPEED_PINCTRL_PIN(U2),
- ASPEED_PINCTRL_PIN(U20),
- ASPEED_PINCTRL_PIN(U21),
- ASPEED_PINCTRL_PIN(U22),
ASPEED_PINCTRL_PIN(U3),
- ASPEED_PINCTRL_PIN(U4),
- ASPEED_PINCTRL_PIN(U5),
- ASPEED_PINCTRL_PIN(V1),
- ASPEED_PINCTRL_PIN(V19),
ASPEED_PINCTRL_PIN(V2),
- ASPEED_PINCTRL_PIN(V20),
- ASPEED_PINCTRL_PIN(V21),
- ASPEED_PINCTRL_PIN(V22),
ASPEED_PINCTRL_PIN(V3),
- ASPEED_PINCTRL_PIN(V4),
- ASPEED_PINCTRL_PIN(V5),
ASPEED_PINCTRL_PIN(V6),
- ASPEED_PINCTRL_PIN(W1),
- ASPEED_PINCTRL_PIN(W19),
ASPEED_PINCTRL_PIN(W2),
- ASPEED_PINCTRL_PIN(W20),
- ASPEED_PINCTRL_PIN(W21),
- ASPEED_PINCTRL_PIN(W22),
ASPEED_PINCTRL_PIN(W3),
- ASPEED_PINCTRL_PIN(W4),
- ASPEED_PINCTRL_PIN(W5),
- ASPEED_PINCTRL_PIN(W6),
- ASPEED_PINCTRL_PIN(Y1),
- ASPEED_PINCTRL_PIN(Y19),
- ASPEED_PINCTRL_PIN(Y2),
- ASPEED_PINCTRL_PIN(Y20),
- ASPEED_PINCTRL_PIN(Y21),
- ASPEED_PINCTRL_PIN(Y22),
ASPEED_PINCTRL_PIN(Y3),
- ASPEED_PINCTRL_PIN(Y4),
- ASPEED_PINCTRL_PIN(Y5),
- ASPEED_PINCTRL_PIN(Y6),
};
static const struct aspeed_pin_group aspeed_g5_groups[] = {
- ASPEED_PINCTRL_GROUP(ACPI),
- ASPEED_PINCTRL_GROUP(ADC0),
- ASPEED_PINCTRL_GROUP(ADC1),
- ASPEED_PINCTRL_GROUP(ADC10),
- ASPEED_PINCTRL_GROUP(ADC11),
- ASPEED_PINCTRL_GROUP(ADC12),
- ASPEED_PINCTRL_GROUP(ADC13),
- ASPEED_PINCTRL_GROUP(ADC14),
- ASPEED_PINCTRL_GROUP(ADC15),
- ASPEED_PINCTRL_GROUP(ADC2),
- ASPEED_PINCTRL_GROUP(ADC3),
- ASPEED_PINCTRL_GROUP(ADC4),
- ASPEED_PINCTRL_GROUP(ADC5),
- ASPEED_PINCTRL_GROUP(ADC6),
- ASPEED_PINCTRL_GROUP(ADC7),
- ASPEED_PINCTRL_GROUP(ADC8),
- ASPEED_PINCTRL_GROUP(ADC9),
- ASPEED_PINCTRL_GROUP(BMCINT),
- ASPEED_PINCTRL_GROUP(DDCCLK),
- ASPEED_PINCTRL_GROUP(DDCDAT),
- ASPEED_PINCTRL_GROUP(ESPI),
- ASPEED_PINCTRL_GROUP(FWSPICS1),
- ASPEED_PINCTRL_GROUP(FWSPICS2),
ASPEED_PINCTRL_GROUP(GPID0),
ASPEED_PINCTRL_GROUP(GPID2),
- ASPEED_PINCTRL_GROUP(GPID4),
- ASPEED_PINCTRL_GROUP(GPID6),
ASPEED_PINCTRL_GROUP(GPIE0),
- ASPEED_PINCTRL_GROUP(GPIE2),
- ASPEED_PINCTRL_GROUP(GPIE4),
- ASPEED_PINCTRL_GROUP(GPIE6),
ASPEED_PINCTRL_GROUP(I2C10),
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
@@ -1996,50 +736,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(I2C7),
ASPEED_PINCTRL_GROUP(I2C8),
ASPEED_PINCTRL_GROUP(I2C9),
- ASPEED_PINCTRL_GROUP(LAD0),
- ASPEED_PINCTRL_GROUP(LAD1),
- ASPEED_PINCTRL_GROUP(LAD2),
- ASPEED_PINCTRL_GROUP(LAD3),
- ASPEED_PINCTRL_GROUP(LCLK),
- ASPEED_PINCTRL_GROUP(LFRAME),
- ASPEED_PINCTRL_GROUP(LPCHC),
- ASPEED_PINCTRL_GROUP(LPCPD),
- ASPEED_PINCTRL_GROUP(LPCPLUS),
- ASPEED_PINCTRL_GROUP(LPCPME),
- ASPEED_PINCTRL_GROUP(LPCRST),
- ASPEED_PINCTRL_GROUP(LPCSMI),
- ASPEED_PINCTRL_GROUP(LSIRQ),
ASPEED_PINCTRL_GROUP(MAC1LINK),
- ASPEED_PINCTRL_GROUP(MAC2LINK),
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
- ASPEED_PINCTRL_GROUP(NCTS1),
- ASPEED_PINCTRL_GROUP(NCTS2),
- ASPEED_PINCTRL_GROUP(NCTS3),
- ASPEED_PINCTRL_GROUP(NCTS4),
- ASPEED_PINCTRL_GROUP(NDCD1),
- ASPEED_PINCTRL_GROUP(NDCD2),
- ASPEED_PINCTRL_GROUP(NDCD3),
- ASPEED_PINCTRL_GROUP(NDCD4),
- ASPEED_PINCTRL_GROUP(NDSR1),
- ASPEED_PINCTRL_GROUP(NDSR2),
- ASPEED_PINCTRL_GROUP(NDSR3),
- ASPEED_PINCTRL_GROUP(NDSR4),
- ASPEED_PINCTRL_GROUP(NDTR1),
- ASPEED_PINCTRL_GROUP(NDTR2),
- ASPEED_PINCTRL_GROUP(NDTR3),
- ASPEED_PINCTRL_GROUP(NDTR4),
- ASPEED_PINCTRL_GROUP(NRI1),
- ASPEED_PINCTRL_GROUP(NRI2),
- ASPEED_PINCTRL_GROUP(NRI3),
- ASPEED_PINCTRL_GROUP(NRI4),
- ASPEED_PINCTRL_GROUP(NRTS1),
- ASPEED_PINCTRL_GROUP(NRTS2),
- ASPEED_PINCTRL_GROUP(NRTS3),
- ASPEED_PINCTRL_GROUP(NRTS4),
ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PEWAKE),
- ASPEED_PINCTRL_GROUP(PNOR),
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM2),
@@ -2052,102 +753,22 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RMII1),
ASPEED_PINCTRL_GROUP(RMII2),
- ASPEED_PINCTRL_GROUP(RXD1),
- ASPEED_PINCTRL_GROUP(RXD2),
- ASPEED_PINCTRL_GROUP(RXD3),
- ASPEED_PINCTRL_GROUP(RXD4),
- ASPEED_PINCTRL_GROUP(SALT1),
- ASPEED_PINCTRL_GROUP(SALT10),
- ASPEED_PINCTRL_GROUP(SALT11),
- ASPEED_PINCTRL_GROUP(SALT12),
- ASPEED_PINCTRL_GROUP(SALT13),
- ASPEED_PINCTRL_GROUP(SALT14),
- ASPEED_PINCTRL_GROUP(SALT2),
- ASPEED_PINCTRL_GROUP(SALT3),
- ASPEED_PINCTRL_GROUP(SALT4),
- ASPEED_PINCTRL_GROUP(SALT5),
- ASPEED_PINCTRL_GROUP(SALT6),
- ASPEED_PINCTRL_GROUP(SALT7),
- ASPEED_PINCTRL_GROUP(SALT8),
- ASPEED_PINCTRL_GROUP(SALT9),
- ASPEED_PINCTRL_GROUP(SCL1),
- ASPEED_PINCTRL_GROUP(SCL2),
ASPEED_PINCTRL_GROUP(SD1),
- ASPEED_PINCTRL_GROUP(SD2),
- ASPEED_PINCTRL_GROUP(SDA1),
- ASPEED_PINCTRL_GROUP(SDA2),
- ASPEED_PINCTRL_GROUP(SGPS1),
- ASPEED_PINCTRL_GROUP(SGPS2),
- ASPEED_PINCTRL_GROUP(SIOONCTRL),
- ASPEED_PINCTRL_GROUP(SIOPBI),
- ASPEED_PINCTRL_GROUP(SIOPBO),
- ASPEED_PINCTRL_GROUP(SIOPWREQ),
- ASPEED_PINCTRL_GROUP(SIOPWRGD),
- ASPEED_PINCTRL_GROUP(SIOS3),
- ASPEED_PINCTRL_GROUP(SIOS5),
- ASPEED_PINCTRL_GROUP(SIOSCI),
ASPEED_PINCTRL_GROUP(SPI1),
- ASPEED_PINCTRL_GROUP(SPI1CS1),
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
- ASPEED_PINCTRL_GROUP(SPI2CK),
- ASPEED_PINCTRL_GROUP(SPI2CS0),
- ASPEED_PINCTRL_GROUP(SPI2CS1),
- ASPEED_PINCTRL_GROUP(SPI2MISO),
- ASPEED_PINCTRL_GROUP(SPI2MOSI),
- ASPEED_PINCTRL_GROUP(TIMER3),
ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8),
- ASPEED_PINCTRL_GROUP(TXD1),
- ASPEED_PINCTRL_GROUP(TXD2),
- ASPEED_PINCTRL_GROUP(TXD3),
- ASPEED_PINCTRL_GROUP(TXD4),
- ASPEED_PINCTRL_GROUP(UART6),
- ASPEED_PINCTRL_GROUP(USBCKI),
ASPEED_PINCTRL_GROUP(VGABIOSROM),
- ASPEED_PINCTRL_GROUP(VGAHS),
- ASPEED_PINCTRL_GROUP(VGAVS),
- ASPEED_PINCTRL_GROUP(VPI24),
- ASPEED_PINCTRL_GROUP(VPO),
- ASPEED_PINCTRL_GROUP(WDTRST1),
- ASPEED_PINCTRL_GROUP(WDTRST2),
};
static const struct aspeed_pin_function aspeed_g5_functions[] = {
- ASPEED_PINCTRL_FUNC(ACPI),
- ASPEED_PINCTRL_FUNC(ADC0),
- ASPEED_PINCTRL_FUNC(ADC1),
- ASPEED_PINCTRL_FUNC(ADC10),
- ASPEED_PINCTRL_FUNC(ADC11),
- ASPEED_PINCTRL_FUNC(ADC12),
- ASPEED_PINCTRL_FUNC(ADC13),
- ASPEED_PINCTRL_FUNC(ADC14),
- ASPEED_PINCTRL_FUNC(ADC15),
- ASPEED_PINCTRL_FUNC(ADC2),
- ASPEED_PINCTRL_FUNC(ADC3),
- ASPEED_PINCTRL_FUNC(ADC4),
- ASPEED_PINCTRL_FUNC(ADC5),
- ASPEED_PINCTRL_FUNC(ADC6),
- ASPEED_PINCTRL_FUNC(ADC7),
- ASPEED_PINCTRL_FUNC(ADC8),
- ASPEED_PINCTRL_FUNC(ADC9),
- ASPEED_PINCTRL_FUNC(BMCINT),
- ASPEED_PINCTRL_FUNC(DDCCLK),
- ASPEED_PINCTRL_FUNC(DDCDAT),
- ASPEED_PINCTRL_FUNC(ESPI),
- ASPEED_PINCTRL_FUNC(FWSPICS1),
- ASPEED_PINCTRL_FUNC(FWSPICS2),
ASPEED_PINCTRL_FUNC(GPID0),
ASPEED_PINCTRL_FUNC(GPID2),
- ASPEED_PINCTRL_FUNC(GPID4),
- ASPEED_PINCTRL_FUNC(GPID6),
ASPEED_PINCTRL_FUNC(GPIE0),
- ASPEED_PINCTRL_FUNC(GPIE2),
- ASPEED_PINCTRL_FUNC(GPIE4),
- ASPEED_PINCTRL_FUNC(GPIE6),
ASPEED_PINCTRL_FUNC(I2C10),
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
@@ -2160,50 +781,11 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(I2C7),
ASPEED_PINCTRL_FUNC(I2C8),
ASPEED_PINCTRL_FUNC(I2C9),
- ASPEED_PINCTRL_FUNC(LAD0),
- ASPEED_PINCTRL_FUNC(LAD1),
- ASPEED_PINCTRL_FUNC(LAD2),
- ASPEED_PINCTRL_FUNC(LAD3),
- ASPEED_PINCTRL_FUNC(LCLK),
- ASPEED_PINCTRL_FUNC(LFRAME),
- ASPEED_PINCTRL_FUNC(LPCHC),
- ASPEED_PINCTRL_FUNC(LPCPD),
- ASPEED_PINCTRL_FUNC(LPCPLUS),
- ASPEED_PINCTRL_FUNC(LPCPME),
- ASPEED_PINCTRL_FUNC(LPCRST),
- ASPEED_PINCTRL_FUNC(LPCSMI),
- ASPEED_PINCTRL_FUNC(LSIRQ),
ASPEED_PINCTRL_FUNC(MAC1LINK),
- ASPEED_PINCTRL_FUNC(MAC2LINK),
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
- ASPEED_PINCTRL_FUNC(NCTS1),
- ASPEED_PINCTRL_FUNC(NCTS2),
- ASPEED_PINCTRL_FUNC(NCTS3),
- ASPEED_PINCTRL_FUNC(NCTS4),
- ASPEED_PINCTRL_FUNC(NDCD1),
- ASPEED_PINCTRL_FUNC(NDCD2),
- ASPEED_PINCTRL_FUNC(NDCD3),
- ASPEED_PINCTRL_FUNC(NDCD4),
- ASPEED_PINCTRL_FUNC(NDSR1),
- ASPEED_PINCTRL_FUNC(NDSR2),
- ASPEED_PINCTRL_FUNC(NDSR3),
- ASPEED_PINCTRL_FUNC(NDSR4),
- ASPEED_PINCTRL_FUNC(NDTR1),
- ASPEED_PINCTRL_FUNC(NDTR2),
- ASPEED_PINCTRL_FUNC(NDTR3),
- ASPEED_PINCTRL_FUNC(NDTR4),
- ASPEED_PINCTRL_FUNC(NRI1),
- ASPEED_PINCTRL_FUNC(NRI2),
- ASPEED_PINCTRL_FUNC(NRI3),
- ASPEED_PINCTRL_FUNC(NRI4),
- ASPEED_PINCTRL_FUNC(NRTS1),
- ASPEED_PINCTRL_FUNC(NRTS2),
- ASPEED_PINCTRL_FUNC(NRTS3),
- ASPEED_PINCTRL_FUNC(NRTS4),
ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PEWAKE),
- ASPEED_PINCTRL_FUNC(PNOR),
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM2),
@@ -2216,68 +798,16 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RMII1),
ASPEED_PINCTRL_FUNC(RMII2),
- ASPEED_PINCTRL_FUNC(RXD1),
- ASPEED_PINCTRL_FUNC(RXD2),
- ASPEED_PINCTRL_FUNC(RXD3),
- ASPEED_PINCTRL_FUNC(RXD4),
- ASPEED_PINCTRL_FUNC(SALT1),
- ASPEED_PINCTRL_FUNC(SALT10),
- ASPEED_PINCTRL_FUNC(SALT11),
- ASPEED_PINCTRL_FUNC(SALT12),
- ASPEED_PINCTRL_FUNC(SALT13),
- ASPEED_PINCTRL_FUNC(SALT14),
- ASPEED_PINCTRL_FUNC(SALT2),
- ASPEED_PINCTRL_FUNC(SALT3),
- ASPEED_PINCTRL_FUNC(SALT4),
- ASPEED_PINCTRL_FUNC(SALT5),
- ASPEED_PINCTRL_FUNC(SALT6),
- ASPEED_PINCTRL_FUNC(SALT7),
- ASPEED_PINCTRL_FUNC(SALT8),
- ASPEED_PINCTRL_FUNC(SALT9),
- ASPEED_PINCTRL_FUNC(SCL1),
- ASPEED_PINCTRL_FUNC(SCL2),
ASPEED_PINCTRL_FUNC(SD1),
- ASPEED_PINCTRL_FUNC(SD2),
- ASPEED_PINCTRL_FUNC(SDA1),
- ASPEED_PINCTRL_FUNC(SDA2),
- ASPEED_PINCTRL_FUNC(SGPS1),
- ASPEED_PINCTRL_FUNC(SGPS2),
- ASPEED_PINCTRL_FUNC(SIOONCTRL),
- ASPEED_PINCTRL_FUNC(SIOPBI),
- ASPEED_PINCTRL_FUNC(SIOPBO),
- ASPEED_PINCTRL_FUNC(SIOPWREQ),
- ASPEED_PINCTRL_FUNC(SIOPWRGD),
- ASPEED_PINCTRL_FUNC(SIOS3),
- ASPEED_PINCTRL_FUNC(SIOS5),
- ASPEED_PINCTRL_FUNC(SIOSCI),
ASPEED_PINCTRL_FUNC(SPI1),
- ASPEED_PINCTRL_FUNC(SPI1CS1),
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
- ASPEED_PINCTRL_FUNC(SPI2CK),
- ASPEED_PINCTRL_FUNC(SPI2CS0),
- ASPEED_PINCTRL_FUNC(SPI2CS1),
- ASPEED_PINCTRL_FUNC(SPI2MISO),
- ASPEED_PINCTRL_FUNC(SPI2MOSI),
- ASPEED_PINCTRL_FUNC(TIMER3),
ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8),
- ASPEED_PINCTRL_FUNC(TXD1),
- ASPEED_PINCTRL_FUNC(TXD2),
- ASPEED_PINCTRL_FUNC(TXD3),
- ASPEED_PINCTRL_FUNC(TXD4),
- ASPEED_PINCTRL_FUNC(UART6),
- ASPEED_PINCTRL_FUNC(USBCKI),
ASPEED_PINCTRL_FUNC(VGABIOSROM),
- ASPEED_PINCTRL_FUNC(VGAHS),
- ASPEED_PINCTRL_FUNC(VGAVS),
- ASPEED_PINCTRL_FUNC(VPI24),
- ASPEED_PINCTRL_FUNC(VPO),
- ASPEED_PINCTRL_FUNC(WDTRST1),
- ASPEED_PINCTRL_FUNC(WDTRST2),
};
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 387b75aebc25..49aeba912531 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -14,10 +14,6 @@
#include "../core.h"
#include "pinctrl-aspeed.h"
-const char *const aspeed_pinmux_ips[] = { "SCU", "SIO", "GFX", "LPC" };
-
-#define SPI1_REG_MASK 0x3000
-
int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
@@ -82,9 +78,7 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
static inline void aspeed_sig_desc_print_val(
const struct aspeed_sig_desc *desc, bool enable, u32 rv)
{
- pr_debug("Want %s%lX[0x%08X]=0x%X, got 0x%X from 0x%08X\n",
- aspeed_pinmux_ips[SIG_DESC_IP_FROM_REG(desc->reg)],
- SIG_DESC_OFFSET_FROM_REG(desc->reg),
+ pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg,
desc->mask, enable ? desc->enable : desc->disable,
(rv & desc->mask) >> __ffs(desc->mask), rv);
}
@@ -111,8 +105,6 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
unsigned int raw;
u32 want;
- WARN_ON(SIG_DESC_IP_FROM_REG(desc->reg) != ASPEED_IP_SCU);
-
if (regmap_read(map, desc->reg, &raw) < 0)
return false;
@@ -150,19 +142,9 @@ static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
- size_t ip = SIG_DESC_IP_FROM_REG(desc->reg);
-
- if (ip == ASPEED_IP_SCU) {
- if (!aspeed_sig_desc_eval(desc, enabled, map))
- return false;
- } else {
- size_t offset = SIG_DESC_OFFSET_FROM_REG(desc->reg);
- const char *ip_name = aspeed_pinmux_ips[ip];
-
- pr_debug("Ignoring configuration of field %s%X[0x%08X]\n",
- ip_name, offset, desc->mask);
- }
+ if (!aspeed_sig_desc_eval(desc, enabled, map))
+ return false;
}
return true;
@@ -180,7 +162,6 @@ static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
*
* @return true if the expression is configured as requested, false otherwise
*/
-
static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
bool enable, struct regmap *map)
{
@@ -189,58 +170,20 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
for (i = 0; i < expr->ndescs; i++) {
bool ret;
const struct aspeed_sig_desc *desc = &expr->descs[i];
-
- size_t offset = SIG_DESC_OFFSET_FROM_REG(desc->reg);
- size_t ip = SIG_DESC_IP_FROM_REG(desc->reg);
- bool is_scu = (ip == ASPEED_IP_SCU);
- const char *ip_name = aspeed_pinmux_ips[ip];
-
u32 pattern = enable ? desc->enable : desc->disable;
- u32 val = (pattern << __ffs(desc->mask));
/*
* Strap registers are configured in hardware or by early-boot
- * firmware. With the exception of SPI1 interface bits, treat
- * them as read-only despite that we can write
+ * firmware. Treat them as read-only despite that we can write
* them. This may mean that certain functions cannot be
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
*/
- if (is_scu && (offset == HW_STRAP2 ||
- (offset == HW_STRAP1 && !(desc->mask & SPI1_REG_MASK))))
+ if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2)
continue;
- /*
- * HW_STRAP1 bits can only be set to 0 by writing 1 into
- * bits of same offset in SCU7C. To configure different SPI1
- * modes, we write 1 to SCU7C[13:12] to clear SPI1 mask to make
- * sure later write to strap register can take effect.
- */
- if (is_scu && offset == HW_STRAP1 &&
- (desc->mask & SPI1_REG_MASK)) {
- ret = regmap_write(map, HW_STRAP1_CLEAR, desc->mask);
- if (ret)
- return false;
- };
-
- /*
- * Sometimes we need help from IP outside the SCU to activate a
- * mux request. Report that we need its cooperation.
- */
- if (enable && !is_scu) {
- pr_debug("Pinmux request for %s requires cooperation of %s IP: Need (%s%X[0x%08X] = 0x%08X\n",
- expr->function, ip_name, ip_name, offset,
- desc->mask, val);
- }
-
- /* And only read/write SCU registers */
- if (!is_scu) {
- pr_debug("Skipping configuration of field %s%X[0x%08X]\n",
- ip_name, offset, desc->mask);
- continue;
- }
-
- ret = regmap_update_bits(map, desc->reg, desc->mask, val) == 0;
+ ret = regmap_update_bits(map, desc->reg, desc->mask,
+ pattern << __ffs(desc->mask)) == 0;
if (!ret)
return ret;
@@ -400,8 +343,6 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
const struct aspeed_sig_expr **funcs;
const struct aspeed_sig_expr ***prios;
- pr_debug("Muxing pin %d for %s\n", pin, pfunc->name);
-
if (!pdesc)
return -EINVAL;
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
index 602b2608ba78..3e72ef8c54bf 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
@@ -232,15 +232,6 @@
* group.
*/
-#define ASPEED_IP_SCU 0
-#define ASPEED_IP_SIO 1
-#define ASPEED_IP_GFX 2
-#define ASPEED_IP_LPC 3
-
-#define SIG_DESC_TO_REG(ip, offset) (((ip) << 24) | (offset))
-#define SIG_DESC_IP_FROM_REG(reg) (((reg) >> 24) & GENMASK(7, 0))
-#define SIG_DESC_OFFSET_FROM_REG(reg) ((reg) & GENMASK(11, 0))
-
/*
* The "Multi-function Pins Mapping and Control" table in the SoC datasheet
* references registers by the device/offset mnemonic. The register macros
@@ -255,7 +246,6 @@
#define SCU3C 0x3C /* System Reset Control/Status Register */
#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
-#define HW_STRAP1_CLEAR 0x7C /* Bits written 1 to are cleared from HW_STRAP1 */
#define SCU80 0x80 /* Multi-function Pin Control #1 */
#define SCU84 0x84 /* Multi-function Pin Control #2 */
#define SCU88 0x88 /* Multi-function Pin Control #3 */
@@ -265,19 +255,13 @@
#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
-#define SCUAC 0xAC /* Multi-function Pin Control #10 */
#define HW_STRAP2 0xD0 /* Strapping */
-#define SIORD30 SIG_DESC_TO_REG(ASPEED_IP_SIO, 0x30)
-
/**
* A signal descriptor, which describes the register, bits and the
* enable/disable values that should be compared or written.
*
- * @reg: Split into three fields:
- * 31:24: IP selector
- * 23:12: Reserved
- * 11:0: Register offset
+ * @reg: The register offset from base in bytes
* @mask: The mask to apply to the register. The lowest set bit of the mask is
* used to derive the shift value.
* @enable: The value that enables the function. Value should be in the LSBs,
@@ -286,7 +270,7 @@
* LSBs, not at the position of the mask.
*/
struct aspeed_sig_desc {
- u32 reg;
+ unsigned int reg;
u32 mask;
u32 enable;
u32 disable;
@@ -581,4 +565,5 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
int aspeed_pinctrl_probe(struct platform_device *pdev,
struct pinctrl_desc *pdesc,
struct aspeed_pinctrl_data *pdata);
+
#endif /* PINCTRL_ASPEED */
--
2.9.3
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