[PATCH linux v3] arm: aspeed: zaius: Disable LPC reset for UART1

[Joel Stanley]

On Wed, Feb 1, 2017 at 11:42 AM, Xo Wang via openbmc
<openbmc at lists.ozlabs.org> wrote:
> Currently, UART1 on Zaius BMC is unusable until brought out of reset by
> powering the host on. In that default reset state, ttyS0 can still be
> opened and UART1 silently drops bytes, which is not obviously expected
> behavior.
>
> Clear the LPC block control bit that enables LPCRST# as a reset source
> for UART1, making UART1 immediately useful in that it won't discard
> bytes.
>
> Signed-off-by: Xo Wang <xow at google.com>

Andrew, Rick, are you guys happy with this now? Can I get an ack or review tag?

Cheers,

Joel

> ---
>  arch/arm/mach-aspeed/aspeed.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
> index 4bd3680d742d..b7022eaa7b5d 100644
> --- a/arch/arm/mach-aspeed/aspeed.c
> +++ b/arch/arm/mach-aspeed/aspeed.c
> @@ -185,6 +185,14 @@ static void __init do_zaius_setup(void)
>
>         /* Set SPI1 CE0 decoding window to 0x30000000 */
>         writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30));
> +
> +       /* Disable default behavior of UART1 being held in reset by LPCRST#.
> +        * By releasing UART1 from being controlled by LPC reset, it becomes
> +        * immediately available regardless of the host being up.
> +        * */
> +       reg = readl(AST_IO(AST_BASE_LPC | 0x98));
> +       /* Clear "Enable UART1 reset source from LPC" */
> +       writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98));
>  }
>
>  static void __init do_witherspoon_setup(void)
> --
> 2.11.0.483.g087da7b7c-goog
>
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