[PATCH linux dev-4.10 01/10] aspeed: barreleye: Remove unnecessary GPIO configuration

[Andrew Jeffery]

These values will be configured by requesting the GPIOs from userspace,
as the GPIO controller plumbs its pin request through the pinctrl
subsystem.

Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
---
 arch/arm/mach-aspeed/aspeed.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 7ac006aaa5f4..6c6bac0c3e63 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -64,13 +64,6 @@ static void __init do_barreleye_setup(void)
 	writel(0x9E82FCE7, AST_IO(AST_BASE_GPIO | 0x00));
 	writel(0x0370E677, AST_IO(AST_BASE_GPIO | 0x04));
 
-	/* SCU setup
-	 *  - GPION must be set to GPIO mode (SCU88[0:7] = 0) on
-	 *    Barreleye so they can be used to read the PCIe inventory
-	 *    status
-	 */
-	writel(0x01C00000, AST_IO(AST_BASE_SCU | 0x88));
-
 	/* To enable GPIOE0 pass through function debounce mode */
 	writel(0x010FFFFF, AST_IO(AST_BASE_SCU | 0xA8));
 
-- 
2.9.3