[PATCH qemu 18/38] aspeed/smc: add a 'sdram_base' property

[Andrew Jeffery]

On Fri, 2016-11-18 at 15:21 +0100, Cédric Le Goater wrote:
> The setting of the DRAM address of the DMA transaction depends on the
> DRAM base address of the SoC, so we add a property to give this
> information to the model.
> 
> Signed-off-by: Cédric Le Goater <clg at kaod.org>

Reviewed-by: Andrew Jeffery <andrew at aj.id.au>

> ---
>  hw/arm/aspeed_soc.c         | 7 +++++++
>  hw/ssi/aspeed_smc.c         | 1 +
>  include/hw/ssi/aspeed_smc.h | 3 +++
>  3 files changed, 11 insertions(+)
> 
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index fcf029f8c1c2..24354f700115 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -276,6 +276,13 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>      }
>  
>      object_property_set_int(OBJECT(&s->fmc), fmc_num_cs, "num-cs", &err);
> +    object_property_set_int(OBJECT(&s->fmc), sc->info->sdram_base, "sdram-base",
> +                            &local_err);
> +    error_propagate(&err, local_err);
> +    if (err) {
> +        error_propagate(errp, err);
> +        return;
> +    }
>      object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err);
>      error_propagate(&err, local_err);
>      if (err) {
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 8e7e3bd9e335..24c78aa57537 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -819,6 +819,7 @@ static const VMStateDescription vmstate_aspeed_smc = {
>  };
>  
>  static Property aspeed_smc_properties[] = {
> +    DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
>      DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
>      DEFINE_PROP_END_OF_LIST(),
>  };
> diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
> index 39ee601940e8..88a904849801 100644
> --- a/include/hw/ssi/aspeed_smc.h
> +++ b/include/hw/ssi/aspeed_smc.h
> @@ -96,6 +96,9 @@ typedef struct AspeedSMCState {
>      uint8_t r_timings;
>      uint8_t conf_enable_w0;
>  
> +    /* for DMA support */
> +    uint64_t sdram_base;
> +
>      AspeedSMCFlash *flashes;
>  } AspeedSMCState;
>  
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