[PATCH qemu 07/38] aspeed: add the definitions for the AST2400 A1 SoC

[Andrew Jeffery]

On Fri, 2016-11-18 at 15:21 +0100, Cédric Le Goater wrote:
> There is not much differences with the A0 revision a part from the DDR
> calibration.
> 
> Signed-off-by: Cédric Le Goater <clg at kaod.org>

Reviewed-by: Andrew Jeffery <andrew at aj.id.au>

> ---
>  hw/arm/aspeed_soc.c          | 10 ++++++++++
>  hw/misc/aspeed_scu.c         |  2 ++
>  hw/misc/aspeed_sdmc.c        |  3 +++
>  include/hw/misc/aspeed_scu.h |  1 +
>  4 files changed, 16 insertions(+)
> 
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 387b712d8fd5..503efe0f5f77 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -59,6 +59,16 @@ static const AspeedSoCInfo aspeed_socs[] = {
>          .fmc_typename = "aspeed.smc.fmc",
>          .spi_typename = aspeed_soc_ast2400_typenames,
>      }, {
> +        .name         = "ast2400-a1",
> +        .cpu_model    = "arm926",
> +        .silicon_rev  = AST2400_A1_SILICON_REV,
> +        .sdram_base   = AST2400_SDRAM_BASE,
> +        .sram_size    = 0x8000,
> +        .spis_num     = 1,
> +        .spi_bases    = aspeed_soc_ast2400_spi_bases,
> +        .fmc_typename = "aspeed.smc.fmc",
> +        .spi_typename = aspeed_soc_ast2400_typenames,
> +    }, {
>          .name         = "ast2400",
>          .cpu_model    = "arm926",
>          .silicon_rev  = AST2400_A0_SILICON_REV,
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index b1f3e6f6b87a..34e86385d837 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -231,6 +231,7 @@ static void aspeed_scu_reset(DeviceState *dev)
>  
>      switch (s->silicon_rev) {
>      case AST2400_A0_SILICON_REV:
> +    case AST2400_A1_SILICON_REV:
>          reset = ast2400_a0_resets;
>          break;
>      case AST2500_A0_SILICON_REV:
> @@ -249,6 +250,7 @@ static void aspeed_scu_reset(DeviceState *dev)
>  
>  static uint32_t aspeed_silicon_revs[] = {
>      AST2400_A0_SILICON_REV,
> +    AST2400_A1_SILICON_REV,
>      AST2500_A0_SILICON_REV,
>      AST2500_A1_SILICON_REV,
>  };
> diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
> index 8830dc084c38..5f3ac0b6f608 100644
> --- a/hw/misc/aspeed_sdmc.c
> +++ b/hw/misc/aspeed_sdmc.c
> @@ -119,6 +119,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
>          /* Make sure readonly bits are kept */
>          switch (s->silicon_rev) {
>          case AST2400_A0_SILICON_REV:
> +        case AST2400_A1_SILICON_REV:
>              data &= ~ASPEED_SDMC_READONLY_MASK;
>              break;
>          case AST2500_A0_SILICON_REV:
> @@ -193,6 +194,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
>      /* Set ram size bit and defaults values */
>      switch (s->silicon_rev) {
>      case AST2400_A0_SILICON_REV:
> +    case AST2400_A1_SILICON_REV:
>          s->regs[R_CONF] |=
>              ASPEED_SDMC_VGA_COMPAT |
>              ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
> @@ -224,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
>  
>      switch (s->silicon_rev) {
>      case AST2400_A0_SILICON_REV:
> +    case AST2400_A1_SILICON_REV:
>          s->ram_bits = ast2400_rambits(s);
>          break;
>      case AST2500_A0_SILICON_REV:
> diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
> index 14ffc43de809..bd4ac013f997 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -32,6 +32,7 @@ typedef struct AspeedSCUState {
>  } AspeedSCUState;
>  
>  #define AST2400_A0_SILICON_REV   0x02000303U
> +#define AST2400_A1_SILICON_REV   0x02010303U
>  #define AST2500_A0_SILICON_REV   0x04000303U
>  #define AST2500_A1_SILICON_REV   0x04010303U
>  
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