[PATCH qemu 19/38] aspeed/smc: add support for DMAs

[Joel Stanley]

On Sat, Nov 19, 2016 at 12:51 AM, Cédric Le Goater <clg at kaod.org> wrote:
> Some of SMC controllers on the Aspeed SoCs support DMA to access the
> flash modules. It can operate in a normal mode, to copy to or from the
> flash module mapping window, or in a checksum calculation mode, to
> evaluate the best clock settings for reads.
>
> When DMA is enabled, a DMA request is built and passed on to a bottom
> half to handle the memory transaction. The CPU is notified of the
> completion with an IRQ if it was enabled.
>
> Signed-off-by: Cédric Le Goater <clg at kaod.org>
> ---
>  hw/ssi/aspeed_smc.c | 234 ++++++++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 227 insertions(+), 7 deletions(-)
>
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 24c78aa57537..9596ea94a3bc 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c

> @@ -685,6 +697,202 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
>      }
>  }
>
> +typedef struct AspeedDmaCo {
> +    AspeedSMCState *s;
> +    int len;
> +    uint32_t flash_addr;
> +    uint32_t dram_addr;
> +    uint32_t checksum;
> +    bool direction;
> +} AspeedDmaCo;

What does the "Co" part mean?

> +
> +static void coroutine_fn aspeed_smc_dma_done(AspeedDmaCo *dmaco)
> +{
> +    AspeedSMCState *s = dmaco->s;
> +
> +    s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
> +    if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
> +        qemu_irq_raise(s->irq);
> +    }
> +}