[PATCH qemu 33/38] wdt: aspeed: use scu to get clock freq
Cédric Le Goater
clg at kaod.org
Sat Nov 19 01:22:13 AEDT 2016
Signed-off-by: Cédric Le Goater <clg at kaod.org>
---
hw/arm/aspeed_soc.c | 2 ++
hw/misc/aspeed_scu.c | 12 ++++++++++++
hw/watchdog/wdt_aspeed.c | 19 +++++++++++++++----
include/hw/misc/aspeed_scu.h | 1 +
include/hw/watchdog/wdt_aspeed.h | 2 ++
5 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 2926ed2dd46d..06c1f03555b1 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -173,6 +173,8 @@ static void aspeed_soc_init(Object *obj)
object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
+ object_property_add_const_link(OBJECT(&s->wdt), "scu", OBJECT(&s->scu),
+ NULL);
}
static int aspeed_fmc_get_cs(AspeedSoCState *s, Error **errp)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index b5efba9121b2..3f577ca12771 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -268,6 +268,18 @@ bool is_supported_silicon_rev(uint32_t silicon_rev)
return false;
}
+#define ASPEED_PLL_25MHZ 25000000
+#define ASPEED_PLL_24MHZ 24000000
+#define ASPEED_PLL_12MHZ 12000000
+
+uint32_t aspeed_scu_get_clk(AspeedSCUState *scu)
+{
+ if (scu->hw_strap1 & AST2400_CLK_25M_IN)
+ return ASPEED_PLL_25MHZ;
+ else
+ return ASPEED_PLL_24MHZ;
+}
+
static void aspeed_scu_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 860d4b73e2b6..276783de90ad 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -7,10 +7,12 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qapi/error.h"
#include "sysemu/watchdog.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/watchdog/wdt_aspeed.h"
+#include "hw/misc/aspeed_scu.h"
#define WDT_IO_REGION_SIZE 0x1000
@@ -56,8 +58,6 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
}
-#define PCLK_HZ 24000000
-
static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size)
{
@@ -82,7 +82,7 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
if (pclk) {
reload = muldiv64(s->reg_reload_value, NANOSECONDS_PER_SECOND,
- PCLK_HZ) ;
+ s->pclk_freq);
} else {
reload = s->reg_reload_value * 1000;
}
@@ -99,7 +99,7 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
if (pclk) {
reload = muldiv64(s->reg_reload_value, NANOSECONDS_PER_SECOND,
- PCLK_HZ);
+ s->pclk_freq);
} else {
reload = s->reg_reload_value * 1000;
}
@@ -177,10 +177,21 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedWDTState *s = ASPEED_WDT(dev);
+ Object *obj;
+ Error *err = NULL;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired,
dev);
+ obj = object_property_get_link(OBJECT(dev), "scu", &err);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'scu' not found: %s",
+ __func__, error_get_pretty(err));
+ return;
+ }
+
+ s->pclk_freq = aspeed_scu_get_clk(ASPEED_SCU(obj));
+
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
TYPE_ASPEED_WDT, WDT_IO_REGION_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index bd4ac013f997..067f9f01819d 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -37,6 +37,7 @@ typedef struct AspeedSCUState {
#define AST2500_A1_SILICON_REV 0x04010303U
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
+extern uint32_t aspeed_scu_get_clk(AspeedSCUState *scu);
/*
* Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index dbf45ae968db..0483335ecee5 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -36,6 +36,8 @@ typedef struct AspeedWDTState {
uint32_t reg_reload_value;
uint32_t reg_restart;
uint32_t reg_ctrl;
+
+ uint32_t pclk_freq;
} AspeedWDTState;
#endif /* ASPEED_WDT_H */
--
2.7.4
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