[PATCH v2 linux dev-4.7 2/7] mtd: spi-nor: aspeed: improve 4 bytes mode

[Joel Stanley]

On Wed, Nov 9, 2016 at 6:45 PM, Cédric Le Goater <clg at kaod.org> wrote:
> The AST2400 SPI flash uses the CE0 control register to set 4Byte mode
> and the AST2500 FMC and AST2400 FMC flash controllers use the CE
> Control register for this purpose or they are strapped by hardware.
>
> Currently, the setting of the CE0 control register is done for all,
> which is incorrect, so fix that to keep only the AST2400 SPI. Luckily,
> the bogus setting has no impact on operations as bit 13 defines a SPI
> clock divisor.
>
> Signed-off-by: Cédric Le Goater <clg at kaod.org>
> ---
>
>  Changes since v1 :
>
>  - added a set_4b() ops
>  - removed the use of SZ_16M

Nice. Now even I understand what it's doing.

Reviewed by: Joel Stanley <joel at jms.id.au>