[PATCH v2 linux dev-4.7 1/7] mtd: spi-nor: aspeed: fix setting of the register control value for writes

[Cédric Le Goater]

The setting of the register control value for writes depends on the
base value which was defined only if the mask applied to it changed
the register control value.

Fix that.

Signed-off-by: Cédric Le Goater <clg at kaod.org>
---

 I kept the info level because nothing wrong is happening. we are just
 possibly changing an optimized value for a non optimized value

 drivers/mtd/spi-nor/aspeed-smc.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index f65379bb2287..75ba73ef0660 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -756,7 +756,7 @@ static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip,
 {
 	struct aspeed_smc_controller *controller = chip->controller;
 	const struct aspeed_smc_info *info = controller->info;
-	u32 reg;
+	u32 reg, base_reg;
 
 	/*
 	 * Always turn on the write enable bit to allow opcodes to be
@@ -789,12 +789,13 @@ static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip,
 	reg = readl(chip->ctl);
 	dev_dbg(controller->dev, "control register: %08x\n", reg);
 
-	if ((reg & CONTROL_SPI_KEEP_MASK) != reg) {
-		chip->ctl_val[smc_base] = reg & CONTROL_SPI_KEEP_MASK;
+	base_reg = reg & CONTROL_SPI_KEEP_MASK;
+	if (base_reg != reg) {
 		dev_info(controller->dev,
 			 "control register changed to: %08x\n",
-			 chip->ctl_val[smc_base]);
+			 base_reg);
 	}
+	chip->ctl_val[smc_base] = base_reg;
 
 	/*
 	 * Retain the prior value of the control register as the
-- 
2.7.4